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zhua
Adventurer
Adventurer
417 Views
Registered: ‎01-31-2020

How to find out error debug signals from implementation error

Hello,

I marked many signals as debug. Then implementation failed with the following error:

zhua_0-1616689755124.png

From the error message I could not tell which debug signal caused it? Does any one has a way to figure it out? I have too many debug signals to try out one at a time.

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hongh
Moderator
Moderator
382 Views
Registered: ‎11-04-2010

Please try to check the opt netlist for the reported LUT connection without sweep stage in opt_design.

Ex: opt_design -retarget -propconst

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zhua
Adventurer
Adventurer
366 Views
Registered: ‎01-31-2020

Hi Hong, I ran the command you mentioned in tcl console. Everything seems fine and I do not see any where indicating any problematic signals. So what should I looking for from the command output? Am I doing correctly as what you suggested? Thanks!
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hongh
Moderator
Moderator
333 Views
Registered: ‎11-04-2010

You can open the opt.dcp and check the connection in the schematic of the reported lut:

select_object [get_cells XX]

F4

click the input pin of the LUT in the schematic.

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zhua
Adventurer
Adventurer
316 Views
Registered: ‎01-31-2020

How should I open a .dcp file? I see *_opt.dcp files under .runs/impl_1. But they are binary. I tried to use Vivado Open File to open it, Vivado said unsupported format. Thanks!
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hongh
Moderator
Moderator
245 Views
Registered: ‎11-04-2010

You can use the below methods to open the design checkpoint file:

1. In TCL CONSOLE, execute the command: "open_checkpoint XX_opt.dcp"

2 File -> Checkpoint -> Open (XX_opt.dcp)

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zhua
Adventurer
Adventurer
168 Views
Registered: ‎01-31-2020

Hi Hong, I

opened my_top_module_opt.dcp. Then clicked ila_core_inst to open the schematic of the ila core. I see all the nets are shown as hidden. Anything am I not doing right? Thanks.ila.JPG

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