12-21-2018 12:32 AM
I'm porting the design to Virtex 7. The utilization is about 25%. Clocks are slow and the timing is clean after synthesis. The congestion is not severe.
But It took extreme time to run routing. It seems there are congestion or hold time problems. I have tried different strategies but doesn't work.
Please help to figure out how to fix it. Thank you.
12-21-2018 12:57 AM
In that case the most likely culprit are your constraint files. I would advise you to review your xdc files.
12-21-2018 01:25 AM
Thank you for reply. What kind of constraint may lead the result? The design and constraints had been verified on other platform.
12-22-2018 10:51 AM
12-22-2018 12:01 PM
01-09-2019 01:40 AM
I have recently written one AR on information for reducing implementation runtime which will be published soon.
Check (Xilinx Answer 50199) to find which particular process in implementation is taking longer runtime from the log file.
If you have an existing routed DCP and would like to make a minor modification in the design then Incremental compile design flow can be used which uses the existing routed DCP as a reference design to speed up place and route runtime.
Check "Incremental compile" topic in Vivado implementation user guide (UG904)
You must provide clean timing constraints, along with timing exceptions, where applicable. Bad constraints result in long runtime, performance issues, and hardware failures.
Common cases are missing CDC exceptions or having incorrect syntax like constraints with missing objects.
Easier to solve timing problems for the tool i.e clean constraints in design will result in reduced runtime.
Querying the large list of nets or pins can be a time-consuming process, so saving the results can speed the design flow when accessing the information repeatedly.
Caching objects in variables can save runtime by reducing the number of queries to the design database.
It is recommended leveraging the relationship between pin (get_pins) and cell (get_cells) objects to improve the runtime for large number of pin queries.
Tip: For timing constraint use -filter IS_SEQUENTIAL with get_cells command to target only sequential elements.
Run DRC report (report_drc) and Methodology report (report_methodology) with the clocking, timing and XDC ruledecks, to identify runtime intensive constraint constructs, non-optimal clocking topologies that can result in more difficult timing closure and constraints issues impacting sign-off timing quality.
It is also recommended to run the Clock Interaction (report_clock_interaction) and CDC (report_cdc) reports to identify paths that are not safely timed or asynchronous crossing that are not properly constrained.
Generating required reports:
You can manage runtime by generating only the reports which are needed.
In project mode, this can be done by using report options in implementation settings.
Check "report strategies" in (UG906) for more details.
Congestion in design will highly impact on runtime. Check (Xilinx Answer 66314) to resolve congestion issues.
Use the '-ultrathreads' option with the 'route_design' command to reduce runtime at expense of repeatability.
If minimal changes (modifying debug probes of ILA, Routing internal net to package pin) is required then ECO flow can help with fast turn-around time.
Check "Vivado ECO flow" in (UG904) for more details.