How to maintain same LUT utilization before after synth and after implementation ?

[ssampath]

HI Friends, 

I want LUT utilization as much as high, For that i used some combinational equation. i got around 95% in after synth design. 

But after implementation this LUT utilization drastically reduced to 30 to 40 % . 

can you please  help on this. 

Question: How to maintain same LUT utilization before after synth and after implementation ?

NOTE: is there any option in implementation to dont opt the design. 

Any suggestion or help is highly appreciated. 

Thank You 

S Sampath 

[rshekhaw]

Hi @ssampath

You can use LOCK_PINS constraint on the LUTs, for information on its usage please check the below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug903-vivado-using-constraints.pdf

Thanks,

Raj

[xilinxacct]

@ssampath

On the surface, this sounds like a 'problem' most people would want to have :-) ... Is what you are not saying, is that some things getting implemented as LUTs but as other hardware (e.g. dsp, bram, etc)? And if so, you are saying the design ends up 'not' being combinational logic after implementation? (Can you post your design? I am curious what exactly you are seeing) Could it be that you synth design is out-of-context, and the implemtation is actually mapping to ports/etc...? Does the design meet timing?

There is a switch that will avoid 'sharing' (fully utilizing) a LUT which will increase the LUT usage, but is typically used only to allow the routes to be a bit faster by wasting some portions of the LUTs. You can try using that.

Hope that helps

If so, please mark as solution accepted. Kudos also welecomed. :-)

[ssampath]

[hemangd]

Hi, 

Is implementation log file shows how LUTs got optimize?

[xilinxacct · Accepted solution]

@ssampath

From the looks of the chart, it looks like it is not coverting LUT to becomes something else. (good news)... So, in the sythesized design is doesn't try to always fully use a LUT, but during implementation, by default, it tries to fully use all the resources of a single LUT to reduce utilization (which is really good for most people). As mentioned, there is a switch in the setting that you can override that behaviour (which 'can' sometimes improve the timing if the routes are overly long due to using a LUT fully, rather than waste some resource. If your design meets timing, you may want to consider this a good thing. If you want to try to get a little faster at the possible expense of some LUTs, turn on the switch in the setting. ( -no_lc )

To see a little more detail on the LUTs, you can see the names like LUT1...LUT6.... if in synthesis you see a lot of LUT1 LUT2 ... these are not fully used, and after implementation, many of the low numbers will not be there, but more LUT6, LUT5... This is a good thing.

Hope that helps

If so, please mark as solution accepted. Kudos also welcomed. :-)

P.S. One other thought... there are no warning that parts of the design are being optimized out, correct? If not, you are good... If so, you may check to see if there is some constant that causes something to disappear.