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How to make communication between KINTEX series board and Cyclone V board based on Trigger signal From Altera Cyclone V board?

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Explorer
Posts: 269
Registered: ‎03-29-2017

How to make communication between KINTEX series board and Cyclone V board based on Trigger signal From Altera Cyclone V board?

 I am trying to make communication between the Altera Cyclone V board and KINTEX custom board [Part Number :XC7k160tffg676-2]

The steps i am follwing as below
   1. Trigger logic in Altera Quartus
        Verilog Code

 module Trigger(
    input clk,
    output reg trig
    );
     always@(posedge clk)
     begin
     trig=clk;
     end
     endmodule

 2.  Based on Trigger, Counter should start [Vivado Design], in clk_in1 i am applying the trigger from Altera board.

 

In vivado, I am getting an Error. I am unable to generate bitstream. Please find the attachment

 

Error.JPG

Observer
Posts: 21
Registered: ‎01-19-2018

Re: How to make communication between KINTEX series board and Cyclone V board based on Trigger signal From Altera Cyclone V board?

@thaus_015,

 

The answer is there is the error message itself.

 

You change your constraint file and add the CLOCK-DEDICATED-ROUTE constraint.

 

https://forums.xilinx.com/t5/Virtex-Family-FPGAs/Is-it-safe-to-set-CLOCK-DEDICATED-ROUTE-FALSE-in-some-cases/td-p/697472

Voyager
Posts: 296
Registered: ‎06-21-2017

Re: How to make communication between KINTEX series board and Cyclone V board based on Trigger signal From Altera Cyclone V board?

Or move the signal to a global clock capable pin.

Explorer
Posts: 269
Registered: ‎03-29-2017

Re: How to make communication between KINTEX series board and Cyclone V board based on Trigger signal From Altera Cyclone V board?

Thanks for your response.

 

I have tried by adding

 

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_in1_IBUF], but even its throwing error.

 

Anyother suggestion.

 

Moderator
Posts: 1,855
Registered: ‎01-16-2013

Re: How to make communication between KINTEX series board and Cyclone V board based on Trigger signal From Altera Cyclone V board?

[ Edited ]

@thaus_015,

 

Can you share the post opt dcp? Also which device are you using?

Check if you are using clock capable pin for IO port clk_in1? I suspect it is not a clock capable pin.

If the port cannot be changed then as stated in error message, CLOCK_DEDICATED_ROUTE should help.

 

If it is a Clock capable pin then check the Global buffers connected to this port are available in the same clock region.

Try locking the Global buffer to same clock region using CLOCK_REGION or LOC constraint. 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug912-vivado-properties.pdf 

 

--Syed

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