06-13-2018 05:16 AM
I am trying to make communication between the Altera Cyclone V board and KINTEX custom board [Part Number :XC7k160tffg676-2]
The steps i am follwing as below
1. Trigger logic in Altera Quartus
output reg trig
2. Based on Trigger, Counter should start [Vivado Design], in clk_in1 i am applying the trigger from Altera board.
In vivado, I am getting an Error. I am unable to generate bitstream. Please find the attachment
06-13-2018 05:37 AM
The answer is there is the error message itself.
You change your constraint file and add the CLOCK-DEDICATED-ROUTE constraint.
06-13-2018 05:58 AM
Thanks for your response.
I have tried by adding
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_in1_IBUF], but even its throwing error.
06-13-2018 09:27 AM - edited 06-13-2018 09:31 AM
Can you share the post opt dcp? Also which device are you using?
Check if you are using clock capable pin for IO port clk_in1? I suspect it is not a clock capable pin.
If the port cannot be changed then as stated in error message, CLOCK_DEDICATED_ROUTE should help.
If it is a Clock capable pin then check the Global buffers connected to this port are available in the same clock region.
Try locking the Global buffer to same clock region using CLOCK_REGION or LOC constraint.