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Visitor
Visitor
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Registered: ‎06-17-2019

How to preserve logic in ISE

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I'm doing a prototype in Spartan6 in ISE.

There are some donttouch modules in ASIC design, so I want them also preserved in circuit.

 

First I use (*KEEP = "TRUE"*) before the module, but I found in map and PAR they still optimize the logic.

So I change it to (* KEEP_HIERARCHY = "TRUE"*) before the module.

But it report some warnings:

MapLib:328 - Block i_top/i_fdes/i_fp/i_xor64_donttouch is  not a recognized logical block. The mapper will continue  to process the design

but there may be design problems if this block does not get trimmed .

Warning : MapLib - Logic Gating not supported for hierarchical instances. Use -ignore_keep_hierarchy. Instance :

 

Is that means the logic is not been preserved??

 

Also I want to ask that how can I know the module I want to preserve is optimized or not??  how can i know the keep property is successfully set or not?

 

 

Thank you!

 

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Moderator
Moderator
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Registered: ‎07-16-2008

The warning looks to indicate you're applying KEEP_HIERACHY to invalid objects. It's expected to be specified on hierarchical instances, whereas i_top/i_fdes/i_fp/i_xor64_donttouch seems to be gating logic.

In ISE, if you want to preserve specific nets/signals, you may apply SAVE NET FLAG constraint.

(* S = "TRUE"*)

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Visitor
Visitor
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Registered: ‎06-17-2019

I also tried (*DONT_TOUCH = TRUE*) before the module, there are no warnings , but I dont know is it works or not..

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Visitor
Visitor
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Registered: ‎06-17-2019

could someone help me ?

 

how can I know the modules are keep or not ?

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Moderator
Moderator
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Registered: ‎01-16-2013

@iamsocute 

 

Post implementation, you can open the design in PlanAhead from ISE and check the modules and its connection.

 

--Syed

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Moderator
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Registered: ‎07-16-2008

The warning looks to indicate you're applying KEEP_HIERACHY to invalid objects. It's expected to be specified on hierarchical instances, whereas i_top/i_fdes/i_fp/i_xor64_donttouch seems to be gating logic.

In ISE, if you want to preserve specific nets/signals, you may apply SAVE NET FLAG constraint.

(* S = "TRUE"*)

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Visitor
Visitor
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Registered: ‎06-17-2019

Thank you  for your reply.

 

I finally find the reason that one input of this module always be zero.

 

But one more question,

I try (DONT_TOUCH = "TRUE") constraint before the wire declaration in donttouch module , is it same as (S = "TRUE")?

 

Best Regards

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Moderator
Moderator
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Registered: ‎11-04-2010

Hi, @iamsocute ,

DONT_TOUCH property is only for Vivado Design Suite, and ISE cannot recognize this property.

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Visitor
Visitor
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Registered: ‎06-17-2019

But  in synthesis log , it prints out "set property DONT_TOUCH = TRUE for signal <o> ". 

And in PlanAhead, there is a "DONT_TOUCH" in attributes property and be selected.

So it makes me confused.

 

Thank you ! 

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Moderator
Moderator
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Registered: ‎11-04-2010

All the supported synthesis attributes in ISE are listed in UG687.

PlanAhead is predecessor for Vivado, and some Vivado proerpty has been added into it for testing purpose. You are not encouraged to use such unsupported attributes in ISE flow.

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Visitor
Visitor
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Registered: ‎06-17-2019

Thank you very much.

 

What's more , is the S property works during the whole process ?

I want to save the signal during the whole process (synthesis, translate , map and PAR)

I used to use KEEP property, but it only works in synthesis process.

 

Best regards.

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Visitor
Visitor
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Registered: ‎06-17-2019

Which user guide should I refer to when I want to attribute in whole process(especially synthesis, MAP and PAR)? 

And where can I report bug ?

I got some PhyDesignRules:367 Warnings when I check the MAP message in Summary.

But in the left "Design" Block, the MAP has a green success notation.

 

Thank you 

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