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jcolli
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Registered: ‎04-05-2016

How to prevent LUT combining

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I am currently designing on an Artix 7.  My design has a large number of single input gates.  I would like for each of theses gates to be placed in an individual LUT6(I get that this isn't horribly space efficient, but that isn't my concern in this design).  It is my understanding that by using -no_lc in synthesis, the single input gates in my design should be placed in this manner. 

 

However, when I use -no_lc, some portion of my single input gates are invariably combined as 2 LUT5's inside of a single LUT6.  Is there something that I am missing here?  Is there some other method that I need to use to prevent these single input gates from being combined?

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avrumw
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Registered: ‎01-23-2009

I think you may be confusing "LUT combining" with "Boolean optimization"

 

LUT combining is when two unrelated functions with less than 2 or 3 inputs are combined into a LUT5 or LUT6 to save space. It is only LUT combining when the functions are unrelated - i.e. they aren't (at least directly) in each others up or down cone of logic.

 

However, whenever you have combinatorial functions feeding other combinatorial functions, the synthesis tool always looks for ways of reducing the critical path - and generally that means combining the logic together in a single LUT.

 

Now lets look at your question... What are "single input gates"? There are only two single input gates - buffers and inverters. Logic buffers (as opposed to clock buffers or I/I buffers) don't have any meaning in FPGAs; the routing fabric is fully buffered, so every route connection is a "buffer". So that leaves inverters. Having back to back inverters is a no-op, so the tools will simply remove them. The only reason people try and have chains of inverters are for delay chains (including oscillators made of delay chains), and there are tons of discussions on them in the forums (most of which advise you not to do this).

 

So, lets ignore single input functions, and look at two input functions

 

assign x=a&b;

assign y=x&c;

assign z=y&d;

 

Its irrelevant how this is coded, and what tool options you are using; the tool sees this as a 4 input AND gate and will put it into one LUT. This is not LUT combining, this is Boolean optimization.

 

The only way I can think to prevent this is to put each of these in an instance of a submodule and set flatten_hierarchy to "none" - this way, the tools will not be able to combine them since it must preserve the hierarchy. You might also be able to manage it through judicious use of the DONT_TOUCH attribute (but I am not certain).

 

But I ask the bigger question - why would you want to prevent it from combining these functions together?

 

Avrum

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3 Replies
avrumw
Expert
Expert
15,224 Views
Registered: ‎01-23-2009

I think you may be confusing "LUT combining" with "Boolean optimization"

 

LUT combining is when two unrelated functions with less than 2 or 3 inputs are combined into a LUT5 or LUT6 to save space. It is only LUT combining when the functions are unrelated - i.e. they aren't (at least directly) in each others up or down cone of logic.

 

However, whenever you have combinatorial functions feeding other combinatorial functions, the synthesis tool always looks for ways of reducing the critical path - and generally that means combining the logic together in a single LUT.

 

Now lets look at your question... What are "single input gates"? There are only two single input gates - buffers and inverters. Logic buffers (as opposed to clock buffers or I/I buffers) don't have any meaning in FPGAs; the routing fabric is fully buffered, so every route connection is a "buffer". So that leaves inverters. Having back to back inverters is a no-op, so the tools will simply remove them. The only reason people try and have chains of inverters are for delay chains (including oscillators made of delay chains), and there are tons of discussions on them in the forums (most of which advise you not to do this).

 

So, lets ignore single input functions, and look at two input functions

 

assign x=a&b;

assign y=x&c;

assign z=y&d;

 

Its irrelevant how this is coded, and what tool options you are using; the tool sees this as a 4 input AND gate and will put it into one LUT. This is not LUT combining, this is Boolean optimization.

 

The only way I can think to prevent this is to put each of these in an instance of a submodule and set flatten_hierarchy to "none" - this way, the tools will not be able to combine them since it must preserve the hierarchy. You might also be able to manage it through judicious use of the DONT_TOUCH attribute (but I am not certain).

 

But I ask the bigger question - why would you want to prevent it from combining these functions together?

 

Avrum

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austin
Scholar
Scholar
8,421 Views
Registered: ‎02-27-2008

j,

 

If the routing resources are dense, a LUT may get used to pass thru a signal (to get to resources).

 

I would not care (do nothing).


Only in extreme cases do you need to intervene in LUT usage and placement (virtually never).

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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jcolli
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Registered: ‎04-05-2016

It looks like I was confusing LUT combining and Boolean optimization.  Thanks for the information

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