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ami.kum
Adventurer
Adventurer
326 Views
Registered: ‎11-08-2018

How to prevent Vivado from removing logic during implementation

I am using Vivado 2020.1 with a Virtex Ultrascale device.  The issue I am facing id the High-Speed I/O IP which is used in RX mode is getting removed during implementation. 

Can I use Don't touch attribute to fix the issue or is there something that is fundamentally wrong with my RTL code which is causing the Vivado implementation to optimize and remove the ip connections? 

I have RX I/O which are input to the FPGA and feed to BRAM FIFO and then the data is being read from FIFOs and used internally within the FPGA.

Attached are pictures from Synthesis and Implementation runs. Note that the implementation run removes the high-speed IP. 

I have a testcase project archive that I can send but unable to attach to this post as it is 21 MB file.

 

Please advise.

systh.jpg
Impl.jpg
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3 Replies
bruce_karaffa
Scholar
Scholar
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Registered: ‎06-21-2017

Have you simulated your design?  Do the data to the FIFOs, the read enable and write enable toggle?  Does the FIFO data effect an output of your FPGA?

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ami.kum
Adventurer
Adventurer
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Registered: ‎11-08-2018

ch0_ca_n, ch0_ca_p, ch1_ca_n, ch1_ca_p, clk_n_bank65, clk_p_bank65 are inputs to the FPGA which feed/connect to the high-speed I/O ip.

The FIFO read and write are always enabled ( do not toggle) as I have the high-speed data coming into the FPGA  and getting stored in the FIFO. Internal to the FPGA the FIFO data is read at 100 Mhz.

The FIFO data is not an output of the FPGA, it is internally used via a state machine. I tried placing a register on the read side of the FIFO but it does not prevent the issue.

Just like, reset and pxi_clk100 are not getting optimized, I would assume the above signals shouldn't get optimized during implementation.

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bruce_karaffa
Scholar
Scholar
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Registered: ‎06-21-2017

Have you simulated this?

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