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Registered: ‎02-05-2010

How to prevent mapping to remove some logic.


I have some problems with mapping. In "physical report" I have lines like those below:

New or modified components:

time2digital_0/USER_LOGIC_I/Inst_CustomLogic/Inst_GeneratoreNcanali/ZeroGenerazione_Canali[3].Inst_GeneratoreSingoloCanale/Inst_ShiftRegister/Mshreg_tempoRitardatoC_3_8| SRL Inferencing          | Area


Removed components:

time2digital_0/USER_LOGIC_I/Inst_CustomLogic/Inst_GeneratoreNcanali/DueGenerazione_Canali[10].Inst_GeneratoreSingoloCanale/Inst_ShiftRegister/tempoRitardatoB_1_3| SmartOpt Trimming


I don't know what the first one means but I'm sure about the second: tha mapping tool removed that signal! Actually it is a redundant signal, I replicated it to avoid too high fanout.

I applied to those signals the attribute "equivalent_register_removal of ... : signal is "no" " but I think that it works only on synthesis.

I also turned OFF  the "Equivalent Register Removal" option.

How can I avoid that map remove some logic? Maybe I can fix it turning on the "retiming" of the global optimization?

Thank you!

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Registered: ‎04-09-2008

Is there a particular reason you think this net's fanout is too high?  Have you looked at the timing report and found the routing delay is too large?  If it's not, then I wouldn't necessarily worry about it.  The more constraints you apply to a design, the longer the implementation runtime.


However, if you are having trouble meeting timing and want to make an attempt to guide MAP to not prune your signal, try using a FROM/TO/THRU constraint in your ucf.  "keep" or "preserve" attributes you use in your code to direct the tools are only used by the synthesizer.  The synthesizer will not forward annotate those to MAP.

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