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Visitor khyu
Visitor
441 Views
Registered: ‎10-28-2018

How to reduce the delay to output I/O

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Hi 

      Delay between the DFF to output I/O is 9.122 , it is too large.

How can I reduce the delay in the implementation?

Thank you

 Delay Type                         Incr (ns)    Path (ns)       Location                         Chip     Netlist Resource(s)
FDCE (Prop_fdce_C_Q) (r) 0.269        6.794            Site: SLICE_X402Y73   SLR0 u_coreb033/u_usbtop/u_DWC_usb3/U_DWC_usb3_npi_noclkrst/U_DWC_usb3_npi_pwrm/instport[0].U_DWC_usb3_pwrm_prt/U_DWC_usb3_pwrm_u3piu/phy_pipe3_tx_stage2_reg[29]/Q
net (fo=2, routed)                 9.122        15.917                                                               ext_u3phychip_pipe3_out_OBUF[24]
OBUF (Prop_obuf_I_O)  (r) 2.246        18.162           Site: AR12                     SLR0    ext_u3phychip_pipe3_out_OBUF[24]_inst/O
net (fo=0)                              0.000       18.162                                                                ext_u3phychip_pipe3_out[24]
                                                                                   Site: AR12 SLR0                          ext_u3phychip_pipe3_out[24]

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Scholar drjohnsmith
Scholar
400 Views
Registered: ‎07-09-2009

Re: How to reduce the delay to output I/O

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The quickest to output signal is to use the IOB registers,

Depending upon the tool your using, IOB=TRUE is the sort of constraint your looking for
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Mentor xilinxacct
Mentor
406 Views
Registered: ‎10-23-2018

Re: How to reduce the delay to output I/O

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@khyu

Have you already applied path constraints? (One trick I have found, is that when you apply the path constraint, don't be greedy. e.g. ask for just something better (e.g. 1 ns) rather than the full amount needed. Sometimes that is enough to allow a timing closure and sometimes get 'more' than what you need.)

If your design uses LUTs, you 'may' get some benefit of setting the -no_lc flag in the synthesis section. (This may use a few more LUTs, but may improve the routing)

Hope that helps

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Scholar drjohnsmith
Scholar
401 Views
Registered: ‎07-09-2009

Re: How to reduce the delay to output I/O

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The quickest to output signal is to use the IOB registers,

Depending upon the tool your using, IOB=TRUE is the sort of constraint your looking for
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Visitor khyu
Visitor
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Registered: ‎10-28-2018

Re: How to reduce the delay to output I/O

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Hi  drjohsmith :

I set IOB property.

set_property IOB "true" [get_cells u_coreb033/u_usbtop/u_DWC_usb3/U_DWC_usb3_npi_noclkrst/U_DWC_usb3_npi_pwrm/instport[0].U_DWC_usb3_pwrm_prt/U_DWC_usb3_pwrm_u3piu/phy_pipe3_tx_stage2_reg*]

 

But I got the warning message.

How can I clean this warning issue

WARNING: [Shape Builder 18-132] Instance u_coreb033/u_usbtop/u_DWC_usb3/U_DWC_usb3_npi_noclkrst/U_DWC_usb3_npi_pwrm/instport[0].U_DWC_usb3_pwrm_prt/U_DWC_usb3_pwrm_u3piu/phy_pipe3_tx_stage2_reg[10] has IOB = TRUE property, but it cannot be placed in an OLOGIC site. Instance u_coreb033/u_usbtop/u_DWC_usb3/U_DWC_usb3_npi_noclkrst/U_DWC_usb3_npi_pwrm/instport[0].U_DWC_usb3_pwrm_prt/U_DWC_usb3_pwrm_u3piu/phy_pipe3_tx_stage2_reg[10] cannot be placed in site OLOGIC_X0Y0 because the output signal of the instance requires general routing to fabric. But the instance can only be routed to delay or I/O site.
. [/home/ittmp1/khyu/fpga/aab033_khyu/VIVADO_FPGA16_t/aab033/constrain/aab033_timing.xdc:123]

 

 

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Visitor khyu
Visitor
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Registered: ‎10-28-2018

Re: How to reduce the delay to output I/O

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Hi :

            My clock is 125Mhz period is 8ns . and output delay is 3ns.

Output signal is register output but the delay between register and I/O is too long 9ns.

So Output delay constrain fail

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Visitor khyu
Visitor
352 Views
Registered: ‎10-28-2018

Re: How to reduce the delay to output I/O

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I know the cause the WARNING: [Shape Builder 18-132] .

Please refer to 

https://www.xilinx.com/support/answers/66668.html

To ensure a register can be successfully be packed into an IOB, make sure that there is only one logical connection between the top-level port and the FF to be packed into the IOB.

After I remove the other loading of output FF .  The output FF can be packed into IOB.