11-26-2017 09:18 PM
I trying to route the clock signal to normal IO pins but design is not implementing means showing error.
I am assigning MRCC pin to routing clock signal.
The error is- "[Shape Builder 18-152] Instance design_1_i/slaveFIFO2b_fpga_top_0/inst/oddr_y failed to join an OLOGICE2 group as required. Reason: Instance design_1_i/slaveFIFO2b_fpga_top_0/inst/oddr_y cannot be placed in site OLOGIC_X0Y0 because the output signal of the cell requires general routing to fabric and cells placed in OLOGIC can only be routed to delay or I/O site".
How to fix this error please suggest me.
Thanks and Best Regards
11-26-2017 10:45 PM - edited 11-26-2017 11:12 PM
Each FPGA has dedicated clock pins, MRCC/SRCC.
For clock input you need to use the clock capable IO, because the clock capable primitives can be accessed through this IO in clock region.
So please change the IO to clock capable and this issue will resolved.
11-27-2017 07:00 AM
The message seems to imply that the output of the ODDR is also used somewhere else in the design - some other process is using the net connected to the Q of the ODDR as an input. This is structurally illegal - the Q output of the ODDR can only go to the OBUF - either directly or through the ODELAY; no other connections are possible.
Look at your code to find out what is using this signal and correct it.
This has nothing to do with whether the pin is clock capable or not; clock capable pins are only required for clock input - a clock output is not special, and can be done through any pin.