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Visitor alienchang
Visitor
4,110 Views
Registered: ‎02-04-2009

How to treat dcm output as different clock group?

Hi ,

 

We use synplify_pro to do synthesis, and then use ISE to do PAR.

There are lots of clock domains in our design.

Some are generated by DCM. 

We wanna treat all clocks as different clock groups (false path).

So, I define clock for DCM's outputs as different clock group in Synplify_pro, and those written out clock constraints are really not relative between each other.

But if I use the synplicity.ucf for PAR (by xilinx ISE), I found ISE will generate another derived clocks instead of using those in synplicity.ucf.

And the ISE derived clocks were treated relative i.e. they are not false paths and will be analyzed.

 

Here is the example:

From <iv> , I found only the derived clocks were analyzed and they were relative!

So, if any path from CLK01 to CLK01_90 will be analyzed instead of false path.

 

<i> sdc for synplify_pro

set period1 12.90
define_clock {p:CLK1}  -name {CLK1}  -period $period1 -clockgroup d1
define_clock {i:BUFG_CLK_01} -name {CLK01} -period $period1 -clockgroup d10

define_clock {i:BUFG_CLK_01_90} -name {CLK01_90} -period $period1 -clockgroup d109 -rise [expr $period1 /4] -fall [expr $period1 *3/4]

 

<ii> synplicity.ucf generated by synplify_pro => synplify_pro will treat them as different group successfully!

NET "BUFG_CLK01_90" TNM_NET = "BUFG_CLK01_90";
TIMESPEC "TS_BUFG_CLK01_90" = PERIOD "BUFG_CLK01_90" 12.900 ns HIGH 50.00%;
NET "BUFG_CLKFB1" TNM_NET = "BUFG_CLKFB1";
TIMESPEC "TS_BUFG_CLKFB1" = PERIOD "BUFG_CLKFB1" 12.900 ns HIGH 50.00%;
NET "CLK1" TNM_NET = "CLK1";
TIMESPEC "TS_CLK1" = PERIOD "CLK1" 12.900 ns HIGH 50.00%;

 

<iii> design.pcf generated by ISE

#clocks in ucf#

TS_BUFG_CLK01_90 = PERIOD TIMEGRP "BUFG_CLK01_90" 12.9 ns HIGH 50%;
TS_BUFG_CLKFB1 = PERIOD TIMEGRP "BUFG_CLKFB1" 12.9 ns HIGH 50%;
TS_CLK1 = PERIOD TIMEGRP "CLK1" 12.9 ns HIGH 50%;

 

#derived clocks#

TS_CLK01 = PERIOD TIMEGRP "CLK01" TS_CLK1 HIGH 50%;
TS_CLK01_90 = PERIOD TIMEGRP "CLK01_90" TS_CLK1 PHASE 3.225 ns HIGH 50%;

<iv> map.mrp => ISE can't treat them as different group ?

  TS_CLK01_90 = PERIOD TIMEGRP "CLK01_90" T | SETUP   |     1.465ns|     7.040ns|       0|           0
  S_CLK1 PHASE 3.225 ns HIGH 50%            | HOLD    |     3.164ns|            |       0|           0

 

  TS_CLK01 = PERIOD TIMEGRP "CLK01" TS_CLK1 | SETUP   |     5.949ns|     6.951ns|       0|           0
   HIGH 50%                                 | HOLD    |     0.190ns|            |       0|           0

 

   TS_CLK1 = PERIOD TIMEGRP "CLK1" 12.9 ns H | N/A     |         N/A|         N/A|     N/A|         N/A
  IGH 50%                                   |         |            |            |        |            

 

  TS_BUFG_CLKFB1 = PERIOD TIMEGRP "BUFG_CLK | N/A     |         N/A|         N/A|     N/A|         N/A
  FB1" 12.9 ns HIGH 50%                     |         |            |            |        |           

 

  TS_BUFG_CLK01_90 = PERIOD TIMEGRP "BUFG_C | N/A     |         N/A|         N/A|     N/A|         N/A
  LK01_90" 12.9 ns HIGH 50%                 |         |            |            |        |           
 

 

 

I know if I define_clock_delay -rise {CLK01} -rise {CLK01_90} false ==> It will generate TIG in ucf and apply to ISE successfully.

But I wonder why I can not use "-clockgroup" to specify clocks to different group!

 

 

Thank you!

Alien

 

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