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Newbie sufyan
Newbie
9,590 Views
Registered: ‎03-03-2009

How to wirte an EDIF file format that is accepted by xilinx tools

I am trying to modify a C to FPGA compiler to output an EDIF format, can any one help me to any documentation explaining the EDIF format accepted by Xilinx tools.

 

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4 Replies
Xilinx Employee
Xilinx Employee
9,576 Views
Registered: ‎01-03-2008

Re: How to wirte an EDIF file format that is accepted by xilinx tools

While you could go out and get the EDIF specification I think that the easiest way is to create a design in HDL, synthesis it and look at the EDIF output.  Just make sure that you have a hiearchical design with busses so that you can see all of the possible constructs.
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Newbie sufyan
Newbie
9,559 Views
Registered: ‎03-03-2009

Re: How to wirte an EDIF file format that is accepted by xilinx tools

Thanks for your reply mcgett, I tried to search for that, the site www.edif.org is no longer exist. do you know where can I get examples and specifications for such thing. It would be very helpful if these examples where xilinx related.
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Xilinx Employee
Xilinx Employee
9,555 Views
Registered: ‎08-07-2007

Re: How to wirte an EDIF file format that is accepted by xilinx tools

 EDIF 2.0.0 is supported by the xilinx tools
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Xilinx Employee
Xilinx Employee
9,551 Views
Registered: ‎01-03-2008

Re: How to wirte an EDIF file format that is accepted by xilinx tools

Most synthesis tools can output EDIF files.  The Xilinx XST synthesis use to have this as an option as well, but I think that it has been removed in the later versions.  There is also. http://en.wikipedia.org/wiki/EDIF
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