I/O Problem

[noami9226@]

Hi Dears,

I have designed  AXI-Interconnect for 4 Masters and 1 Slave using SystemVerilog. At the time of the design implementation, I  got this error as shown in the screenshot below: The I/O of the design is more than I/O of the FPGA board.

How can I solve this issue?

Regards.

[bruce_karaffa · Accepted solution]

If you really have 399 IOs, you must either change your design to use fewer IOs or use a board that provides more user IOs.