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Participant
Participant
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Registered: ‎10-31-2019

I/O Problem

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Hi Dears,

I have designed  AXI-Interconnect for 4 Masters and 1 Slave using SystemVerilog. At the time of the design implementation, I  got this error as shown in the screenshot below: The I/O of the design is more than I/O of the FPGA board.

How can I solve this issue?

Regards.

 

Untitled.jpg

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Registered: ‎06-21-2017

If you really have 399 IOs, you must either change your design to use fewer IOs or use a board that provides more user IOs.

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Highlighted
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Registered: ‎06-21-2017

If you really have 399 IOs, you must either change your design to use fewer IOs or use a board that provides more user IOs.

View solution in original post

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