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356 Views
Registered: ‎06-21-2017

I/O Standards in Red

I have a design where all I/O standards are defined in the xdc file.  A snippet of the file:

set_property IOSTANDARD RSDS_25 [get_ports data_clk*]
set_property IOSTANDARD RSDS_25 [get_ports even_data*]
set_property IOSTANDARD RSDS_25 [get_ports odd_data*]
set_property IOSTANDARD RSDS_25 [get_ports frm_clk*]
set_property DIFF_TERM true [get_ports data_clk*]
set_property DIFF_TERM true [get_ports even_data*]
set_property DIFF_TERM true [get_ports odd_data*]
set_property DIFF_TERM true [get_ports frm_clk*]

Vivado reads the file as indicated by the impl_1_place_report as shown below:

| Y18        | data_clk1B_p    | High Range | IO_L13P_T2_MRCC_14           | INPUT         | RSDS_25     |      14 |            |      | 100 Ohm Differential |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
| Y19        | data_clk1B_n    | High Range | IO_L13N_T2_MRCC_14           | INPUT         | RSDS_25     |      14 |            |      | 100 Ohm Differential |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
| Y20        |                 | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                      |                      |    2.50 |            |           |          |      |                  |              |                   |              |
| Y21        | odd_data1_p[4]  | High Range | IO_L9P_T1_DQS_14             | INPUT         | RSDS_25     |      14 |            |      | 100 Ohm Differential |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
| Y22        | odd_data1_n[4]  | High Range | IO_L9N_T1_DQS_D13_14         | INPUT         | RSDS_25     |      14 |            |      | 100 Ohm Differential |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |

The bitstream is generated with no errors or critical warnings.  The I/O standards in the I/O Ports tab are all red.  This seems to have started when I migrated to 2019.1 from 2017.2.  Any ideas what I can check? Personally, I think the red is kind of cheerful, but my boss is the nervous type.

8 Replies
Xilinx Employee
Xilinx Employee
318 Views
Registered: ‎05-08-2012

Re: I/O Standards in Red

Hi @bruce_karaffa 

Generally when there are ports highlighted in red in the I/O Ports or Package Pins tabs, you should be able to hover the mouse over these to have a message pop up which indicates a possible problem. Is that the case here? Also, could you provide the coulumn headers for the IO report. I suspect this could have to do with the DIFF_TERM property. There are violations if this is not set correctly, and this property should be migrated to DIFF_TERM_ADV for UltraScale devices.


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Xilinx Employee
Xilinx Employee
301 Views
Registered: ‎05-22-2018

Re: I/O Standards in Red

Hi @bruce_karaffa ,

There might be onr of the two reason for that as mentioned below:

1.)If the IO bank name is hilighted in Red, then  Displays the I/O banks available in the device and a red circle
indicates a failure:

red1Capture.JPG

 

2.) Or in 7 series devices, Zynq-7000 UltraScale devices, UltraScale+ devices, and Zynq UltraScale+ MPSoCs, all I/O ports must have explicit values for the PACKAGE_PIN and IOSTANDARD constraints to generate a bitstream file. In the I/O Ports window, the word default is displayed in red to indicate that these values must be applied manually. You must apply extra care when assigning I/O
standards, because these devices have Low and High voltage I/O banks.

For reference check page no.37 and 79 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug899-vivado-io-clock-planning.pdf

Thanks,

Raj

247 Views
Registered: ‎06-21-2017

Re: I/O Standards in Red

@rshekhawI opened the Noise report.  Nothing in that report is highlighted in red.  The FPGA is a xc7a100tfgg484-2, 7 series, not Ultrascale.  The bitstreeam generates without errors or critical warnings.   Differential input signals LVDS_25 and RSDS_25 are on 2.5V banks with differential terminators enabled in the xdc file. 

@marcbHovering over any of the red highlighted areas does little.  No messages.  Hovering over one of the I/O stds showing an asterisk does nothing. Hovering over one of the red highlighted IO STDs without an asterisk shows the IO STD in black.  It goes back to red when the cursor is moved.  The I/O Ports report showing column headers is below.

red.png

The differential terminators are ebaled in the xdc file as shown below.

# Clock input
set_property IOSTANDARD LVDS_25 [get_ports clk50_p]
set_property DIFF_TERM TRUE [get_ports clk50_p]
set_property DIFF_TERM TRUE [get_ports clk50_n]

# DCON
set_property IOSTANDARD LVCMOS18 [get_ports Data_Out*]
set_property IOSTANDARD LVCMOS18 [get_ports Data_Clock]
set_property IOSTANDARD LVCMOS18 [get_ports Data_Valid]
set_property IOSTANDARD LVCMOS18 [get_ports Tx_toDCON]
set_property IOSTANDARD LVCMOS18 [get_ports Rx_fromDCON]
set_property IOSTANDARD LVCMOS18 [get_ports ping]
set_property IOSTANDARD LVCMOS18 [get_ports DCON_reset]

# ADC data
set_property IOSTANDARD RSDS_25 [get_ports data_clk*]
set_property IOSTANDARD RSDS_25 [get_ports even_data*]
set_property IOSTANDARD RSDS_25 [get_ports odd_data*]
set_property IOSTANDARD RSDS_25 [get_ports frm_clk*]
set_property DIFF_TERM true [get_ports data_clk*]
set_property DIFF_TERM true [get_ports even_data*]
set_property DIFF_TERM true [get_ports odd_data*]
set_property DIFF_TERM true [get_ports frm_clk*]

@chloe-104You have done nothing but exactly repeat what others have said, then added a spam link.  You will be reported.

0 Kudos
Xilinx Employee
Xilinx Employee
232 Views
Registered: ‎05-08-2012

Re: I/O Standards in Red

Hi @bruce_karaffa 

Thanks for the image. The RSDS_25 values look to have an asterisk (*), which should indicate a default value. However, I see that you have set these via constraints. Have the constraints not been saved to the project yet? Also, if you enter the following command in an open netlist, is there any messaging indicating that the IOSTANDARD is not used?

set_property IOSTANDARD RSDS_25 [get_ports even_data*]

Does setting these individually help?

set_property IOSTANDARD RSDS_25 [get_ports even_data[0]]


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------------------------------------------------------------------------- 

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0 Kudos
222 Views
Registered: ‎06-21-2017

Re: I/O Standards in Red

I tried setting some of the signals explicitly.  It makes no difference.  I can try setting them all individually Monday.  I'll get back to you on this.  The RSDS signals do have an asterisk.  RSDS is not the normal default for differential signals, I thought LVDS was.  In any case, the signals are all showing up in the place_report_io file as expected.  I have a similar project with LVDS IO that also shows red asterisks. 

The constraints file is saved to the project.  If I edit it and re-save, the source scanner runs and my design goes out of date. 

0 Kudos
199 Views
Registered: ‎01-22-2015

Re: I/O Standards in Red

@bruce_karaffa 

-some other things to check/try:

1)  "Rules for Combining I/O Standards in the Same Bank" shown on page 97 of UG471 (v1.10).

2) curly braces:

set_property IOSTANDARD RSDS_25 [get_ports {even_data[*]}]

Mark

 

141 Views
Registered: ‎06-21-2017

Re: I/O Standards in Red

Kudos all around.  I added individual IO _STANDARD statements {with curly braces}.  Everything is still red.  On the other hand, the io_placed.rpt report has the IO standards I ask for on the pins I want, nothing is listed as default in that file,  the bitstream builds and my office mate has been running with variants of these bitstreams for a week or so.  I don't want to close this since it has no answer.  On the other hand, I need to focus on things that are more obviously broken.

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Xilinx Employee
Xilinx Employee
110 Views
Registered: ‎05-08-2012

Re: I/O Standards in Red

Hi @bruce_karaffa 

This would probably be easier to debug with the netlist. Is a DCP available?


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