IBUF AND IBUFG ISSUE

[volta]

Hi,

I have implemented my design and to drive an external clock signal into the FPGA the tools have placed an IBUF followed by an IBUFG in series as it is show in the schematic.

I find this a little redundant because in theory only one IBUFG should be necessary to drive an external clock signal into the global clock net of the FPGA.

Is really necessary to use the IBUFG preceded by an IBUF or is only needed to use a single IBUFG?

[balkris]

Yes, the IBUFG needs to connect to a BUFG (or BUFR or other clock resource). In general, though, you don't need to instantiate either the IBUFG or the BUFG; the tools will infer them.

[volta]

Great!

I see your point, however I have made a mistake in my original question. Once I have implemented my design the tools have placed and IBUF followed by a BUFG and never uses an IBUFG.

Reading your answer I wonder if there is a solution that is better than the other.

What is the difference between using an IBUF or an IBUFG?

Thanks

[thakurr]

Hi @volta

>>What is the difference between using an IBUF or an IBUFG?

Refer the below link, page 89:

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

There's nothing essentially different between an IBUF and an IBUFG.  However if you instantiate an IBUFG, the tools will guarantee that the pad driving the IBUFG is global clock-capable.

Regards

Rohit

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[avrumw]

(I really hate the IBUFG) - there is NO SUCH CELL! As far as I know there never has been.

The IBUFG was a short hand for "I want an input buffer (IBUF) and it is my intent to place it on a clock capable pin". Older tools would give an error if an IBUFG was LOC'ed to a non-clock capable pin. But with the newer technologies, the types of clock capable pins have changed and hence the IBUFG is nothing more than a simple IBUF.

An IBUFG is not now, nor has it ever been a "global clock buffer" - it is an input buffer. If you want the signal on a global clock, it must pass through a BUFG. If you do not instantiate one in your design, then the tools will infer a BUFG on any signal connected to an input (through either an IBUF or and IBUFG) that drives the clock pins of clocked cells in your design.

So, the IBUF -> IBUFG combination you see in your schematic is correct.

Avrum

[syedz]

@volta,

If your query is addressed then please close this thread by marking the post which helped as "Accept as Solution"

--Syed

[volta]

Hi,

Thank you very much, now I understand  better the difference between IBUG, BUFG and IBUFG, and dealing with these concepts I found an interesting question.

As far as I know, the BUFG (BUFGCTRL) are all placed in the middle of the FPGA, but I have just realized there are other elements like BUFHCE that I have never seen before. I see in the documentation that it is named (Horizontal Clock Bluffer).

Is the BUFG for the vertical lines of the dedicated clock route and the BUFHCE for the horizontal lines?

Thanks

[avrumw]

The 32 BUFG drive the 32 vertical clock spines of the global clock network (and nothing else).

At the intersection of the vertical clock spine and the center of each clock region, there are 12 BUFH, which can drive a clock from any one of the vertical spines into the clock region. From there, the clocks drive all the clocked elements in the clock region.

The concept of selecting which global clocks enter which clock region have existed for many generations, but in earlier incarnations they could only be driven by the vertical clock spines, and hence they were not user visible, had no user visible features (like clock enable), and hence did they have a name. In the later technologies, the BUFH has a CE for clock gating (the BUFHCE) and can also be driven directly (from the MMCM/PLL in the same clock region as the BUFH, as well the clock capable I/O in the same region and the one horizontally adjacent to it [or something like that]). Because of this, the cell is now user visible and has a name (BUFH).

Note, regardless of whether you instantiate one or not, all global clocks go through a BUFH to get to the clocked elements; the tools implement this invisibly during the clock routing phase. You can see this if you look at the detailed route view after implementation...

Avrum

[volta]

Hi @avrumw,

At the moment I imagine the FPGA clock network as a grill, where the vertical lines are managed by the BUFG while the horizontal are managed by the BUFH.

But after reading your message again I am starting to think that BUFG is to drive a signal into the clock line, while BUFH is to drive that signal into one of the different clock regions of the FPGA.

This is a little confusing to me, I don’t know if I have understood it well.

Thanks,

Volta.

[avrumw]

What I am describing is the architecture of the Virtex-6 and 7-series (and sort of Virtex-5). The architecture of UltraScale and UltraScale+ is different.

The clocking architecture is described in quite a bit of detail in the Clocking Resources Users Guide for each architecture; for the 7 series, this is UG472.

Avrum