04-23-2019 02:12 PM
I want to change the EMBV - PYTHON-1300-C SDSoC platform reference design to fit my custom pcb. On it, the clock and some data lines from the camera lvds interface are inverted.
Therefore I replaced the IBUFDS for the incoming clock with a IBUFGDS_DIFF_OUT
When I try to run the implementation, I get the following error:
[Place 30-642] Placement Validity Check : Failed to find legal placement. Reason: Could not legally place instance <truncated>gen_hs_clk_in.gen_regional_hs_clk_in.BUFIO_regional_hs_clk_in at BUFIO_X1Y11 since it belongs to a shape containing instance <truncated>gen_hs_clk_in.gen_diff_hs_clk_in.IBUFGDS_DIFF_OUT_inst/IBUFDS. The shape requires relative placement between <truncated>gen_hs_clk_in.gen_regional_hs_clk_in.BUFIO_regional_hs_clk_in and <truncated>gen_hs_clk_in.gen_diff_hs_clk_in.IBUFGDS_DIFF_OUT_inst/IBUFDS that can not be honoured because it would result in an invalid location for <truncated>gen_hs_clk_in.gen_diff_hs_clk_in.IBUFGDS_DIFF_OUT_inst/IBUFDS. The unplaced cells are: Cell <truncated>gen_hs_clk_in.gen_regional_hs_clk_in.BUFIO_regional_hs_clk_in of type BUFIO placed at site RPM_X0Y0 (BUFIO) Cell <truncated>gen_hs_clk_in.gen_diff_hs_clk_in.IBUFGDS_DIFF_OUT_inst/IBUFDS of type IBUFDS placed at site RPM_X1Y-2 (INBUF_EN) Cell IO_PYTHON_CAM_clk_out_p placed at site RPM_X1Y-2 Cell <truncated>gen_hs_clk_in.gen_diff_hs_clk_in.IBUFGDS_DIFF_OUT_inst/IBUFDS_0 of type IBUFDS placed at site RPM_X1Y-1 (INBUF_DCIEN) Cell IO_PYTHON_CAM_clk_out_n placed at site RPM_X1Y-1 Shape dimensions: Width = 2, Height = 3 <truncated> = embv_top_i/python1300c_catpure/onsemi_python_cam_0/U0/onsemi_vita_cam_v3_1_S00_AXI_inst/onsemi_vita_cam_core_inst/vita_iserdes_v5.vita_iserdes/serdesclockgen.ic/
I attach the diff file for the vdhl file, my pin constrains and the schematic snippet. Due to licencing from Cypress, I cannot share the vdhl file, but you can download the design from the first link download page (free account registration required).
Basically I understand that both entities wants to occupy the same tile but why does it work with a IBUFDS and not a IBUFDS_DIFF_OUT. I did not find a UserGuide telling me that I cannot connect the OB port of a IBUFDS_DIFF_OUT with a BUFIO/BUFMR.
842782 is about a similar issue but I cannot understand why the solution (using a mrcc pin and then the topology should be ok) is not fitting my design.
The pins used are U18/U19 which are MRCC on the Z7020 CLG 400. I use a Vivado 2015.4 on a Ubuntu 14.04 VM and a Parallella board with a self build dautherboard.
Using an inverter is not an option, because routing is done completely in the RIO area to introduce not much latency - is that right? Sorry I am getting started with FPGAs atm.
Can someone please help me out? Is it possible to connect it the way I intend it to work or where is the issue here. The error looks to generic for me, not telling why it is not possible to place both entities.
04-24-2019 08:35 AM
Desperately trying to solve the issue I removed the BUFIO between the IBUFDS_DIFF_OUT OB Pin and the rest of the logic by simply renaming the out port of the IOBUF to that of the BUFIO and comment the BUFIO out.
With this config it does pass the place and route but I cannot imagine it to be valid, because:
Meditating over the error message, I looked at the device representation of the "successful" run and more questions arises:
I tried to LOC constrain the BUFIO to the BUFIO tile next to the used BUFR but this fails as well.
It seems that the Package Pin assignment with the implicit LOC constrain maybe causes issue, but when I try to assign a pin after synthesis, I can't because U18/U19 is no valid location for the clock signal
[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance <trunc>.BUFIO_test on site TIEOFF_X78Y76. The location site type does not match the instance type. Instance <trunc>.BUFIO_test belongs to a shape with reference instance <trunc>.IBUFGDS_DIFF_OUT_inst/IBUFDS. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["/home/parallella/Xilinx/SDSoC/2015.4/platforms/embv_top/vivado/embv_top.srcs/constrs_1/imports/constrs/pin_embv.xdc":82] [Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance <trunc>.BUFIO_test on site TIEOFF_X78Y76. The location site type does not match the instance type. Instance <trunc>.BUFIO_test belongs to a shape with reference instance <trunc>.IBUFGDS_DIFF_OUT_inst/IBUFDS. Shape elements have relative placement respect to each other. The invalid location might results from a constraint on any of the instance in the shape. ["/home/parallella/Xilinx/SDSoC/2015.4/platforms/embv_top/vivado/embv_top.srcs/constrs_1/imports/constrs/pin_embv.xdc":83] [Vivado 12-2285] Cannot set LOC property of instance '<trunc>.BUFIO_test', Could not legally place instance <trunc>.BUFIO_test at BUFIO_X1Y4 since it belongs to a shape containing instance <trunc>.IBUFGDS_DIFF_OUT_inst/IBUFDS. The shape requires relative placement between <trunc>.BUFIO_test and <trunc>.IBUFGDS_DIFF_OUT_inst/IBUFDS that can not be honoured because it would result in an invalid location for <trunc>.IBUFGDS_DIFF_OUT_inst/IBUFDS. ["/home/parallella/Xilinx/SDSoC/2015.4/platforms/embv_top/vivado/embv_top.srcs/constrs_1/imports/constrs/pin_embv.xdc":138] <trunc> = embv_top_i/python1300c_catpure/onsemi_python_cam_0/U0/onsemi_vita_cam_v3_1_S00_AXI_inst/onsemi_vita_cam_core_inst/vita_iserdes_v5.vita_iserdes/serdesclockgen.ic/gen_hs_clk_in.gen_diff_hs_clk_in
I would really appreciate your help on that.
04-25-2019 11:29 AM - edited 04-25-2019 11:30 AM
Okay, now it is getting really strange:
I replaced the BUFIO with a BUFR at the same clock region as the other BUFR being used.
Now it does route and the timings seems plausible.
Here is my snippet:
gen_regional_hs_clk_in: if (USE_HS_REGIONAL_CLK = TRUE) generate -- uses BUFIO because the only clocked instances with this clock are in the IO column -- is limited to one clockregion -- BUFR_regional_hs_clk_in : BUFR -- generic map ( -- BUFR_DIVIDE => "BYPASS", -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" -- SIM_DEVICE => "7SERIES" -- Must be set to "7SERIES" -- ) -- port map ( -- O => clk_tmp, -- 1-bit output: Clock output port -- CE => one, -- 1-bit input: Active high, clock enable (Divided modes only) -- CLR => zero, -- 1-bit input: Active high, asynchronous clear (Divided modes only) -- I => hsinclk -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect -- ); BUFIO_regional_hs_clk_in : BUFIO port map ( O => clk_tmp, -- Clock buffer output I => hsinclk -- Clock buffer input ); CLK <= clk_tmp; CLKb <= clk_tmp; end generate;
(The commented out BUFR is the one I added)
Is it possible, that only the (differential) buffer output of the positive pad is routed to the BUFIO? There is nothing mentioned in the Zynq-7000-TRM or UG472_7Series_Clocking. If so, this would be the worst critical warning / error output I ever got from a compiler. (and I am coming with a C++ background)
For my application, the LVDS interface clock is at maximum 72 MHz DDR so using a BUFR seems to be in specification XC7Z020-Data-Sheet (p. 52 table 68 and 69), right?
But this might change in the future (when switching from 72 MHz single ended to 300 MHz LVDS input clock for the device connected to the FPGA), so I would appreciate a working solution with the LVDS working at full speed. (as in xapp585).
Has somebody an educated guess whats wrong here?