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Adventurer
Adventurer
2,951 Views
Registered: ‎08-12-2010

ILA problem: ila present on synthesis and implementation but hardware manager cannot detect it

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Hello,

I have a problem trying to implement an ila on a design with the zynq 7010.

Yesterday I started successfully checking 3-4 signals, but today adding new signals I'm not able to get a bitstream with the ila.

The signals I want to check are coming from some internal IP blocks. I marked the internal nets as debug without creating an internal ila. Then, I used the set up debug mode to implement the ila on the top level and i can see the ila and the debug hub on the schematic, but when I create the bitstream the hardware manager says this:

 

WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
...
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z010_1 and the probes file(s) /home/berta/Vivado/EPMF/EPMF.runs/impl_1/System_wrapper.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 1 ILA core(s) and 0 VIO core(s).
Resolution:
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

 

The clock I'm using is the 100MHz system clock generated by the zynq as shown in the attached picture.

Attached youalso find the constraint file with the ila constraint generated automatically by Vivado. They should work, but...

 

During the write bitstreatm phase, Vivado sent me a warning saying that there are some no routable loads. Probably this is the signal of the problem, but I don't know why the problem is present now.

 

Where is my error?

 

Thanks

Claudio

 

ila.png
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Xilinx Employee
Xilinx Employee
4,767 Views
Registered: ‎09-20-2012

Hi @bertac

 

Please check this AR https://www.xilinx.com/support/answers/59457.html

 

You need to use SDK to program the PL.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
4,768 Views
Registered: ‎09-20-2012

Hi @bertac

 

Please check this AR https://www.xilinx.com/support/answers/59457.html

 

You need to use SDK to program the PL.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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Adventurer
Adventurer
2,925 Views
Registered: ‎08-12-2010

Hi @vemulad,

thank you for your answer, now finally it works.

Anyway, simply programming the zynq with the SDK in not enough.

 

What I have had to do is:

1) program the zynq with the SDK (I opened the hardware manager and refreshed it to see if the debug core was detected, but unsuccessfully)

2) start a test software with the SDK 

3) refresh the hardware manager

Only after that the debug core has been detected and loaded

Is it a bug of the hardware manager?

 

Thanks a lot 

Claudio

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