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Contributor
Contributor
460 Views
Registered: ‎12-23-2019

IO Clock Placer Failed and BUFG usage

Hi,

I have got two IO Clock Placer Failed one of them

[Place 30-575] Sub-optimal placement for a clock capable IO pin and MMCM pair other one is

[Place 30-150] Sub-optimal placement for an MMCM-BUFG component pair.

Then I look at the Utilization report. I saw 2 over usage. BUFGCTRL 41 (xc7z100ffg900-2L have 36 BUFGCTRL ) and BUFG 36 (xc7z100ffg900-2L have 32 BUFG). 

How can I fix this error?

How can I reduce usage of BUFGCTRL and BUFG?

Thanks for help.

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Xilinx Employee
Xilinx Employee
381 Views
Registered: ‎05-08-2012

Re: IO Clock Placer Failed and BUFG usage

Hi @mustafa_d 

These messages usually include more information which would be important for resolving the issue. First, the description can indicate possible causes. I believe one of these tends to indicate possible issues with using "non clock capable" IO pins. Is this the case?

Also, there should be a fairly long list of rules. Just search for the word "fail" to see if any rules are violated.

For the total utilization, Vivado Synthesis also has an option "-bufg" which gives a threshold on the total number of BUFGs that can be inferred. This can be lowered if needed.

As well, other buffer types can be used if it makes sense. An example would be using a BUFR if all the clock loads from a clock only need to reside in one clock region. More information on the buffer types can be found from the Clocking Resources Guide.

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf#page=52

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Contributor
Contributor
348 Views
Registered: ‎12-23-2019

Re: IO Clock Placer Failed and BUFG usage

I seeing two clock rule one of them rule_mmcm_mmcm and second one is rule_mmcm_bufg but this two clock status showing PASS.

I saw sythesis setting -bufg but this default value 12 I used 36 in my project.

How can I reduce bufg usage?

Is there any general method for this situation?

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Moderator
Moderator
344 Views
Registered: ‎01-16-2013

Re: IO Clock Placer Failed and BUFG usage

@mustafa_d 

 

Open the synthesized design and run the following to commands from TCL console:

1. opt_design

2. place_ports

 

Share the vivado.log file. The BUFG are normally inserted on clock path to take the clock nets. Does your design require high BUFG usage?

If you are sure you do not want BUFG on some specific paths then you can insert CLOCK_BUFFER_TYPE attribute set to none

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug912-vivado-properties.pdf#page=164 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Contributor
Contributor
309 Views
Registered: ‎12-23-2019

Re: IO Clock Placer Failed and BUFG usage

I find the which nets use BUFG and implement your following command CLOCK_BUFFER_TYPE but BUFG number not change BUFH number increase (I used BUFH). Then I look at the schemetic and I saw BUFG and BUFH connect cascade together.

How can I solve this problem?

Thanks for help

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-08-2012

Re: IO Clock Placer Failed and BUFG usage

Hi @mustafa_d 

Regarding the synthesis -bug option, if you would like less BUFGs inferred, you could change the value from the default (12), to some lower value such as 2 or 4 depending on the design needs.

Also, can you verify that the CLOCK_BUFFER_TYPE that you are setting has been applied? From an open netlist (synthesis or implementation), you can check with the following command:

get_property CLOCK_BUFFER_TYPE [get_nets <net_name_you_want_to_check>]

The property will be applied in the step that you set it to. If the XDC is used in synthesis, you should see the property applied after synthesis. If the XDC constraint is only used in implementation, the property would only be seen after the next completed stage, for example opt_design and later netlists.

uploading the project might help if there are still problems.

 

 

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Contributor
Contributor
261 Views
Registered: ‎12-23-2019

Re: IO Clock Placer Failed and BUFG usage

CLOCK_BUFFER_TYPE applied on synthesis state, I checked. But bufg number remain same because bufg and our  CLOCK_BUFFER_TYPE constrait connect cascade. The number of bufg does not decrease. because of this reason I still have a problem.

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Xilinx Employee
Xilinx Employee
196 Views
Registered: ‎05-08-2012

Re: IO Clock Placer Failed and BUFG usage

Hi @mustafa_d 

I would suggest attaching the Vivado project so that the community can suggest a resolution.

It sounds like the constraint is not working as expected, but typically there would be messaging if this were the case. 

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Contributor
Contributor
174 Views
Registered: ‎12-23-2019

Re: IO Clock Placer Failed and BUFG usage

Hi @marcb 

I can not share Vivado project because of safety issue. I wrote constrait like following

set property CLOCK_BUFFER_TYPE BUFH [get_nets <net name>]

after this wrote project have two net one of them bufg version other one is our constrait type.

Constrait seems like works properly, because it is insert bufh relaited net.

Thanks for help

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Xilinx Employee
Xilinx Employee
107 Views
Registered: ‎05-22-2018

Re: IO Clock Placer Failed and BUFG usage

Hi @mustafa_d ,

Can you please share the Vivado.log reporting the complete error message?

Also share the vivado version you are working with.

 

Thanks,

Raj

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