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Visitor
Visitor
12,688 Views
Registered: ‎10-16-2014

IO Placement is infeasible

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hello everyone, I have got this message when trying to implement my design: http://pastebin.com/DtBraWQW what i have to do in order to sort everything out? thank you in advance
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Professor
Professor
21,332 Views
Registered: ‎08-14-2007

It looks like the problem is the IO standard of LVCMOS18 (low-voltage CMOS with 1.8V Vcco supply) when you're already using all available banks with some other Vcco voltage.  Note that LVCMOS18 is also the default IO standard for 7-series devices if you don't specify it in the constraints.  So either you need to take another look at your I/O banking to find a solution for grouping pins that results in a legal placement, or you need to change the voltage standard for the unplaceable pins to match the available bank voltages.

-- Gabor

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Xilinx Employee
Xilinx Employee
12,681 Views
Registered: ‎02-16-2014

Hi,

 

This error may occur if the design uses more I/Os than the available in the selected device and package.

Please check the number of top level ports used and check whether the correct device and package are selected.

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Visitor
Visitor
12,675 Views
Registered: ‎10-16-2014
Can I say to vivado to let those terminal unconnected?
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Xilinx Employee
Xilinx Employee
12,672 Views
Registered: ‎07-11-2011

Hi,

 

Comment out unrequired external interfae ports in your top level and declare them as signals or wires and make necessary connections so that they will not be trimmed out.

If you really require them for external interface recheck your design for total needed pins available pins and select a bigger FPGA

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Visitor
Visitor
12,661 Views
Registered: ‎10-16-2014
Sounds like a workaround :\ Can I add options to my constraint file?
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Professor
Professor
21,333 Views
Registered: ‎08-14-2007

It looks like the problem is the IO standard of LVCMOS18 (low-voltage CMOS with 1.8V Vcco supply) when you're already using all available banks with some other Vcco voltage.  Note that LVCMOS18 is also the default IO standard for 7-series devices if you don't specify it in the constraints.  So either you need to take another look at your I/O banking to find a solution for grouping pins that results in a legal placement, or you need to change the voltage standard for the unplaceable pins to match the available bank voltages.

-- Gabor

View solution in original post

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Visitor
Visitor
12,631 Views
Registered: ‎10-16-2014
Thank you gszakacs. Your solution solved my specific problem
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