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Contributor
Contributor
1,656 Views
Registered: ‎12-24-2017

IO placement is infeasible.

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I tried to set on pins oledrgb and wifi module instead of on dedicated slots so I made them external and set the xdc file but the problem is that for some reason it gives me error.

 

[Place 30-58] IO placement is infeasible. Number of unplaced terminals (16) is greater than number of available sites (0).
The following are banks with available pins:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 16 sites.
Term: PmodOLEDrgb_out_0_pin10_io
Term: PmodOLEDrgb_out_0_pin1_io
Term: PmodOLEDrgb_out_0_pin2_io
Term: PmodOLEDrgb_out_0_pin3_io
Term: PmodOLEDrgb_out_0_pin4_io
Term: PmodOLEDrgb_out_0_pin7_io
Term: PmodOLEDrgb_out_0_pin8_io
Term: PmodOLEDrgb_out_0_pin9_io
Term: Pmod_out_0_pin10_io
Term: Pmod_out_0_pin1_io
Term: Pmod_out_0_pin2_io
Term: Pmod_out_0_pin3_io
Term: Pmod_out_0_pin4_io
Term: Pmod_out_0_pin7_io
Term: Pmod_out_0_pin8_io
Term: and Pmod_out_0_pin9_io

 

I put the design on Mega

https://mega.nz/#!oplR1LCB!hg1SL4OnOltJ9Bwu9Tgrf59--2JGIraXZWLBlJ29UOg

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Moderator
Moderator
2,031 Views
Registered: ‎01-16-2013

Re: IO placement is infeasible.

Jump to solution

@tester11,

 

Check this AR:

https://www.xilinx.com/support/answers/56354.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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6 Replies
Scholar jmcclusk
Scholar
1,518 Views
Registered: ‎02-24-2014

Re: IO placement is infeasible.

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you have overloaded your design with too many IO.   you probably defined new IO pins in the design, and forgot to delete the old assignments.

Don't forget to close a thread when possible by accepting a post as a solution.
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Moderator
Moderator
1,471 Views
Registered: ‎01-16-2013

Re: IO placement is infeasible.

Jump to solution

@tester11,

 

If your query is addressed then Can you please close this thread by marking the above post of @jmcclusk as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Contributor
Contributor
1,464 Views
Registered: ‎12-24-2017

Re: IO placement is infeasible.

Jump to solution

Now I am facing this error,

[DRC UCIO-1] Unconstrained Logical Port: 85 out of 215 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: GPIO_tri_o[3:0], leds_4bits_tri_io[31:0], ext_spi_clk_0, PmodOLEDrgb_out_0_pin10_io, PmodOLEDrgb_out_0_pin1_io, PmodOLEDrgb_out_0_pin2_io, PmodOLEDrgb_out_0_pin3_io, PmodOLEDrgb_out_0_pin4_io, PmodOLEDrgb_out_0_pin7_io, PmodOLEDrgb_out_0_pin8_io, PmodOLEDrgb_out_0_pin9_io, Pmod_out_0_pin10_io, Pmod_out_0_pin1_io, Pmod_out_0_pin2_io, Pmod_out_0_pin3_io... and (the first 15 of 20 listed).

So I run this command set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

but I don't know how to save it in a file and link it to the write_bitstream.In Xilinx documentation it says that I should choose in Generate Tcl script in Project tab but I don't have it.

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Moderator
Moderator
2,032 Views
Registered: ‎01-16-2013

Re: IO placement is infeasible.

Jump to solution

@tester11,

 

Check this AR:

https://www.xilinx.com/support/answers/56354.html

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Contributor
Contributor
1,453 Views
Registered: ‎12-24-2017

Re: IO placement is infeasible.

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This helped but in the SDK I get an error in xstatus.h even if I cleaned the project 

https://image.prntscr.com/image/4ciWWAr0RQOEw1bilagNGw.png

The source code folder has an X on it that shows there is an error in a file but no file has an X on it showing that there is an error..

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Moderator
Moderator
1,447 Views
Registered: ‎01-16-2013

Re: IO placement is infeasible.

Jump to solution

@tester11,

 

Can you please create a new forum post for SDK issue. Also since the implementation issue is resolved, please close this thread by marking the post which helped as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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