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Visitor
Visitor
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Registered: ‎07-02-2019

IOB=TRUE fails

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Hi,

I would like to know what are the requirements for using IOB=TRUE constraint on a register. I have not found any hints in the ug* documents.

I am getting warnings like this:

CRITICAL WARNING: [Place 30-73] Invalid constraint on register 'i_system_wrapper/system_i/sc_fxgen_1/U0/fxout2_reg[0]'. It has the property IOB=TRUE, but it is not driving or driven by any IO element.

WARNING: [DRC PLIO-6] Placement Constraints Check for IO constraints: Invalid constraint on register i_system_wrapper/system_i/sc_fxgen_1/U0/fxout2_reg[0]. It has the property IOB=TRUE, but it is not driving or driven by any IO element.

The register in question is defined as 

signal fxout2 : std_logic_vector(15 downto 0);

and used for nothing else than writing to some GPIO ports (the PMOD-GPIO ports of a ZCU102). The idea is to minimize skew over the port lines by the IOB constraint.

Any advice is welcome.

Thank you, and best regards,

Erik

 

 

 

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Moderator
Moderator
342 Views
Registered: ‎01-16-2013

@e_heinz 

 

The common issue is due to not having a single net connection between IO port and flop. Check this AR which might be helpful:

https://www.xilinx.com/support/answers/66668.html 

 

Check page 244 in below user guide to know syntax details with examples:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=244 

 

Can you show us the post-synthesis connection between IO port and the flop connected to it?

 

--Syed

 

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Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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Highlighted
Moderator
Moderator
343 Views
Registered: ‎01-16-2013

@e_heinz 

 

The common issue is due to not having a single net connection between IO port and flop. Check this AR which might be helpful:

https://www.xilinx.com/support/answers/66668.html 

 

Check page 244 in below user guide to know syntax details with examples:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug912-vivado-properties.pdf#page=244 

 

Can you show us the post-synthesis connection between IO port and the flop connected to it?

 

--Syed

 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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323 Views
Registered: ‎01-22-2015

@e_heinz 

Be sure to note from references given by syedz that IOB=TRUE can be placed on either a port or on a register.  When placed on a port, it will pull a register attached to the port into the IOB.

Cheers,
Mark

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Visitor
Visitor
300 Views
Registered: ‎07-02-2019

Thanks for the valuable responses.

The problem was indeed, that the register was not directly connected to IO. I had not been aware of the fact, that the port definition of the VHDL module produces a register on it's own:

vivado.png

 

 

 

 

 

 

 

 

 

 

When I apply the IOB constraint to the port register fx_reg, everything works as expected.

Best regards,

Erik

 

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288 Views
Registered: ‎01-22-2015

Erik,

I had not been aware of the fact, that the port definition of the VHDL module produces a register on it's own:
This is not entirely correct.  What's happening is the following.  When you assign a value to the port inside a VHDL clocked process then you get a register which has the name of the port.

Also, I notice that you originally tried to set IOB=TRUE on fxout2_reg(*).  That is, you thought that fxout2_reg(*) was driving the port - but it is driving the port through a LUT.  It is bad practice to drive a port from/through a LUT because you will be sending glitches out of the FPGA.  Make sure you drive ports directly from a register.

Cheers,
Mark