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sebo
Voyager
Voyager
613 Views
Registered: ‎03-17-2011

IOB = TRUE property

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Hello,

I have set an attribute like this in my VHDL:

attribute IOB : string;
-- Place the register connected to ACK in the input logic site
attribute IOB of ACK : signal is "TRUE";

I'd like to know how to check if this directive has been correctly implemented. So far, I have found this in the synthesis report of my IP:

INFO: [Synth 8-5534] Detected attribute (* iob = "TRUE" *) [.....srcs/sources_1/bd/system/ipshared/4ae6/src/ip_x.vhd:79]

 

Thanks.

--Sebastien
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sebo
Voyager
Voyager
514 Views
Registered: ‎03-17-2011

These are clarifying information.

On my side, I could verify the xdc property was take into account when opening the implementation and use the tcl commande report_datasheet. In the report, I could see the following

clk_in | ACK | FDRE (IO) | - | -0.789 (r) | FAST | 2.482 (r) | SLOW | |
So, the xdc property works. but somehow the attribute in the RTL code was either ignored or not propagated at top level.

I must add the code I'm referring to is located within an IP core I've packaged myself. So maybe my packaging process is missing something.

 

--Sebastien

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hongh
Moderator
Moderator
603 Views
Registered: ‎11-04-2010

You can open the synthesized design and check the IOB property of the port in TCL CONSOLE with the below command.

Ex: get_property IOB [gt_ports  ACK ]

The return value is expected to be true

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sebo
Voyager
Voyager
595 Views
Registered: ‎03-17-2011

Can I do it when the implementation is opened? When I do it, I get nothing in response to the command.

I thought I could see this in the opened implementation as this directivement is actually implemented at placement stage...

Same behavior in opened synthesized design...

--Sebastien
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sebo
Voyager
Voyager
576 Views
Registered: ‎03-17-2011

So I added the following constraint in the xdc:

set_property IOB TRUE [get_ports {ACK}]

And I could check in the implemented design that the get_property returns TRUE.

I wonder why the attribute constraint in the VHDL is not propagated later on. Do you have an explanation?

 

Thanks.

s/

--Sebastien
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amaccre
Moderator
Moderator
553 Views
Registered: ‎04-24-2013

HI @sebo ,

Setting the IOB property tells the placer to try to place FFs in I/O Logic instead of the fabric slice. 

This property must be assigned to the register and not to the port.

Using the BFT example design if you apply the following:

set_property IOB true [get_cells wbDataForInputReg_reg]

Then you can see that the register has been place in the I/O Logic when you look in the Device view.
See the attached screen shots.

Capture.JPG

Capture1.JPG

You can also query the valuer via the tcl command:

get_property IOB [get_cells wbDataForInputReg_reg]
TRUE

Best Regards
Aidan

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Capture.JPG
Capture1.JPG
sebo
Voyager
Voyager
544 Views
Registered: ‎03-17-2011

Hello @amaccre 

I'm using 2018.3 and I looked at the the documentation related to my version : UG912 (v2018.3) January 14, 2019 .

In the IOB section, I read this:

 IOB directs the Vivado tool to place a register that is connected to the specified port into the input or output logic block. Place this attribute on a port, connected to a register that you want to place into the I/O block

Even the syntax example after are in line with this text.

So I guessed I got it okay with my my constraint on the port and not the register.

Now, I got no error during the implementation but I'm still looking on how to check whether this constraint has been followd or not by the tool.

 

--Sebastien
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drjohnsmith
Teacher
Teacher
543 Views
Registered: ‎07-09-2009

These links might help

its all abotu getting the attribute onto the right part of the design, and not over righting the attribute later in your XDC.

https://www.xilinx.com/support/answers/66668.html

https://forums.xilinx.com/t5/Implementation/set-property-IOB-for-a-port/td-p/851473

 

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avrumw
Guide
Guide
529 Views
Registered: ‎01-23-2009

We have to be careful about the port and the register.

The attribute itself causes the register (which is a cell) to be placed in the IOB. To do this there are a number of requirements

  • Output port
    • The register feeds the input of the OBUF directly or through an ODELAY (if one exists in this technology and bank)
    • The register does not feed anything else
      • This includes itself, or any other OBUF
    • If the output is tristated, and both the T and the O register in the IOB are used, they must use the same clock (I think - at least in some of the older technologies)
  • Input port
    • The output of the IBUF must feed the input of the register, directly or through an IDELAY (if it exists)

In all cases, the register must be flagged to be packed into the register.

In some of the oldest versions of Vivado, you had to put the IOB property on the register. This could get messy if the register was buried deep in the hierarchy and you were trying to do this from the XDC.

In all newer versions of Vivado, the property can be applied either to the register or to the port. When applied to the port, the tool would really trace it back to the register. I don't know if the property is ever actually truly applied to the port, or if the tool propagates it backward and only applies it to the register. Consequently, querying the IOB property of the port after synthesis/implementation may not necessarily be an indication as to whether your VHDL attribute actually got into the design - you should query the register.

If you are doing this in the RTL it is probably a better idea to attach the attribute to the register. If you are doing it in the XDC it is certainly easier to do on the port.

In ISE there was a report that was generated by default that told you which ports have IOB registers and which don't. I don't think Vivado generates one of those by default, but I believe there is a report that you can request to generate this, but it is actually a Tcl script (from the Tcl store). Certainly, on a port by port basis you can inspect the placed result to see if the register was packed in the IOB (as was shown by @amaccre ).

Avrum

sebo
Voyager
Voyager
515 Views
Registered: ‎03-17-2011

These are clarifying information.

On my side, I could verify the xdc property was take into account when opening the implementation and use the tcl commande report_datasheet. In the report, I could see the following

clk_in | ACK | FDRE (IO) | - | -0.789 (r) | FAST | 2.482 (r) | SLOW | |
So, the xdc property works. but somehow the attribute in the RTL code was either ignored or not propagated at top level.

I must add the code I'm referring to is located within an IP core I've packaged myself. So maybe my packaging process is missing something.

 

--Sebastien

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