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Observer doovie
Observer
7,600 Views
Registered: ‎03-20-2013

IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Hi There,


I have several registered I/Os that I want to pack into the IOBs.  For reference I'm using a spartan 3a-dsp.  To that end I've been using the constraint:

 

net foo loc = [some pin];

inst foo IOB = true;

 

When I look at the IOB report in ISE I see the various nets, but the "reg(s)" column is blank for every one.  After poking around the forums I tried enabling the -pr flag for outputs only in the mapping properties.  As soon as I did that the reg(s) column filled up with "OFF1", which is what I'd expect.  I've attached two screen shots of the report using identical ucf files (as per the constraints shown above).  One with -pr enabled and one without.  I'd call it a day, except that I'd like the ability to control which I/Os are register packed and the -pr flag seems to do it indescriminently.  Additionally if you take a look at the screen shots you'll notice that "sram_chip_we" never gets register packed (or at least never gets a "OFF1" in the reg(s) column) with or without -pr enabled.  Any thoughts?  I assume that the reg(s) column is indicative of whether or not register packing is actually taking place.  Perhaps this is misguided?  Thanks a lot,


D

Iob report with pr enabled.png
iob report without pr enabled.png
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1 Solution

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Xilinx Employee
Xilinx Employee
9,984 Views
Registered: ‎07-01-2008

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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You need to apply the IOB constraint to the FF instance not the net name. You can get that name by clicking on the FF BEL displayed in your 2nd image which is a Logic Block Editor image of the slice contents. The name will appear in the history window below if you click on the BEL just right. It can be a little fussy. You can also see a list of the BEL nmaes in the slice attribute window.

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Xilinx Employee
Xilinx Employee
7,596 Views
Registered: ‎07-01-2008

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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You need to apply the IOB constraints to the FF instance not to the nets. You seem to be doing that but under the assumption that the instance name and net name are the same. Check the .bld file (ngdbuild log file) to see if your constraints were rejected for not matching any instances. If so, then you need to determine what the actual instance names are.

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Observer doovie
Observer
7,590 Views
Registered: ‎03-20-2013

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Thanks for the fast reply.  I checked the .bld file and didn't see anything regarding the constraints being rejected.  No errors/warnings.  Any other suggestions?  Thanks,


D

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Xilinx Employee
Xilinx Employee
7,582 Views
Registered: ‎07-01-2008

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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I'd still recommend that you check the name of the FF instances so that the IOB constraints are applied properly. It occurs to me now that your constraints may be matching instances other than FFs and so being silently ignored.

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Observer doovie
Observer
7,575 Views
Registered: ‎03-20-2013

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Thanks for the reply.  You'll have to forgive the naive question, but how do I go about checking that name of the flip flop instances?  Thanks!

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Xilinx Employee
Xilinx Employee
7,569 Views
Registered: ‎07-01-2008

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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You can examine the design in FPGA Editor. Search for the IOB by name using the pad net name. You can trace the the connectivity to the FF BEL from there. You can also use the list window  or the Find window to search for BELs by name. If yo prefer to work with the logical design (pre-map) you can use PlanAhead.

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Observer doovie
Observer
7,540 Views
Registered: ‎03-20-2013

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Thanks for the info.  Finally had a chance to deal with it today.  I'm a little confused as to what I'm seeing.  I'm attaching two screenshots -- one of the IOB and one of the source to the IOB.  I can see that register packing isn't happening (or at least it certainly doesn't appear that way to me).  I also see the signal "_m_sram_chip_addr<0>" leaving the first flop and showing up at the IOB.  Is this the net I should be applying the IOB true constraint to?  Thanks so much.


D

IOB.png
Source.png
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Xilinx Employee
Xilinx Employee
9,985 Views
Registered: ‎07-01-2008

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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You need to apply the IOB constraint to the FF instance not the net name. You can get that name by clicking on the FF BEL displayed in your 2nd image which is a Logic Block Editor image of the slice contents. The name will appear in the history window below if you click on the BEL just right. It can be a little fussy. You can also see a list of the BEL nmaes in the slice attribute window.

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Observer doovie
Observer
7,509 Views
Registered: ‎03-20-2013

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Thanks so much for the info.  I went ahead and based on the attached screenshot placed the following constraint in my ucf:

 

inst "bigBoy/mem/sram_ctrl/sram_chip_addr<1>" iob = true;

 

When I run translate I get the following error:

 

ERROR:ConstraintSystem:59 - Constraint <inst
"bigBoy/mem/sram_ctrl/sram_chip_addr<1>" iob = true;>
[board_test_top_new.ucf(51)]: INST "bigBoy/mem/sram_ctrl/sram_chip_addr<1>"
not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.

 

Obviously I'm doing something wrong here...  Any suggestions?  Thanks and sorry this is taking so long!

 

Screen Shot 2013-06-10 at 12.17.08 PM.png
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Observer doovie
Observer
7,508 Views
Registered: ‎03-20-2013

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Ah! Got it.  Should be using the BEL name as you've stated... Not the component name shown in the dialog at the bottom of the previous screenshot.  Thank you for your help!

 

For future reference is this really the tool flow that I should be using?  First implement the design, then see what BEL name the tools have chosen, and then set the constraint?  Not a huge deal, but is there a way to know apriori what the name assigned to the BEL will be?  This could be a cumbersome flow for several hundred I/Os.  Thanks!

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Xilinx Employee
Xilinx Employee
2,267 Views
Registered: ‎07-01-2008

Re: IOB register packing -- works with -pr flag enabled, but not with IOB = true.

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Usually the synthesis tool will apply the IOB constraint. Or you can use PlanAhead. Because of the work I do I'm more comfortable in the back end tools so I steered you that way.

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