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Adventurer
Adventurer
1,842 Views
Registered: ‎02-08-2013

IODELAY_GROUP problem with a block design

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I get the below error during implementation. Is a block design that includes a master and slave AXI C2C blocks for AXI pass through along will accessing some additional components in the block (UARTs, REGs). The s_aresetn and m_aresetn are tied together but I don't think the RST the error is referring to. It appears the group name "C2C_PHY_group" has been shared between the two C2C blocks and probably should be different. I can't find any way to change this group name. What are my options? 

 

 

[DRC PLIDC-3] IDELAYCTRLs in same group have conflicting connections: IDELAYCTRL cells 'u_axi_block_wrapper/axi_block_i/axi_chip2chip_master/inst/master_fpga_gen.axi_chip2chip_master_phy_inst/master_sio_phy.axi_chip2chip_sio_input_inst/idelayctrl_gen.IDELAYCTRL_inst' and 'u_axi_block_wrapper/axi_block_i/axi_chip2chip_slave/inst/slave_fpga_gen.axi_chip2chip_slave_phy_inst/slave_sio_phy.axi_chip2chip_sio_input_inst/idelayctrl_gen.IDELAYCTRL_inst' have same IODELAY_GROUP 'C2C_PHY_group' but their RST signals are different

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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1 Solution

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Moderator
Moderator
2,993 Views
Registered: ‎05-31-2017

Re: IODELAY_GROUP problem with a block design

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Hi @rayhaynes,

 

Please check this AR#64542

https://www.xilinx.com/support/answers/64542.html

 

Hope it helps.

~Shameer.

 

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to the post which you think is helpful and reply oriented.

 

6 Replies
Voyager
Voyager
1,835 Views
Registered: ‎06-24-2013

Re: IODELAY_GROUP problem with a block design

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Hey @rayhaynes,

 

I think your diagnosis is spot on, the IP related constraints will create a group with this name and nobody considered the case that a Master and Slave (or several Masters/Slaves) would share a design.

 

I can't find any way to change this group name.

I don't think this is customizable a the block design level.

 

What are my options?

Probably the only option is to copy the IP into your project and modify at least one entity to use a different group name.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
Moderator
Moderator
2,994 Views
Registered: ‎05-31-2017

Re: IODELAY_GROUP problem with a block design

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Hi @rayhaynes,

 

Please check this AR#64542

https://www.xilinx.com/support/answers/64542.html

 

Hope it helps.

~Shameer.

 

Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to the post which you think is helpful and reply oriented.

 

Adventurer
Adventurer
1,744 Views
Registered: ‎02-08-2013

Re: IODELAY_GROUP problem with a block design

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It appears I marked this as the solution too soon. The AR talks about the SelectIO Wizard IP core but this is different. All the IP appears to be encrypted and the only place the IODELAY_GROUP appears where I can modify it is in the axi_chip2chip_slave_ip_sim_netlist.vhdl. I assume this file is only for simulation. So now what are my options?
Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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Adventurer
Adventurer
1,742 Views
Registered: ‎02-08-2013

Re: IODELAY_GROUP problem with a block design

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@shameera
It appears I marked this as the solution too soon. The AR talks about the SelectIO Wizard IP core but this is different. All the IP appears to be encrypted and the only place the IODELAY_GROUP appears where I can modify it is in the axi_chip2chip_slave_ip_sim_netlist.vhdl. I assume this file is only for simulation. So now what are my options?
Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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Xilinx Employee
Xilinx Employee
1,716 Views
Registered: ‎09-20-2012

Re: IODELAY_GROUP problem with a block design

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Hi @rayhaynes

 

You can apply the property from XDC file. Open the synthesized design, get the names of IDELAYCTRL/IODELAY cells and then set the property on these cells in XDC.

Thanks,
Deepika.
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Adventurer
Adventurer
1,707 Views
Registered: ‎02-08-2013

Re: IODELAY_GROUP problem with a block design

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Ok, the suggestion from @vemulad did fix the problem. But let elaborate on the steps to do so.

In my case I had 2 idelay blocks who's IODELAY_GROUP parameters where named the same. I needed to change one of the names.

 

Open the synthesized design

Following the path listed in the error message to one of the offending elements, navigate down the Netlist tree to that element. Click on that element. 

Then in the Cell Properties box click on the Properties tab. In that listing of properties you should see the offending property and assigned name. Just change the name, say by adding a 1 to it.

Click on Run Implementation and select Reset and Re-run.

It will then prompt you to save the new constraint created by the name change above. Then I think you'll be good to go.

 

Regards, Ray Haynes, Ostendo Technologies, Inc. Carlsbad, CA
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