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reshmaakhil
Explorer
Explorer
935 Views
Registered: ‎12-05-2016

IOSTANDARD is showing invalid even though correct one is assigned

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Hi all,

I am using Xilinx Vivado 2020.1 version. While trying to do pin mapping for my design even though the IOSTANDARD is correct, its showing invalid(red color). When The same project tried in Vivado 2017.1, I was able to do pin mapping & successfully generated bit stream. 

Note:

1. If I am using an already generated XDC file I am able to generate the bitstream. 

2. Tried in different PCs with same vivado version.

Any help is appreciated. 

Regards,

Reshma R 

1 Solution

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reshmaakhil
Explorer
Explorer
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Registered: ‎12-05-2016

 

Hi all,

Even though IOSTANDARD is appearing in red color I am able to generate the bit stream. 

As markg@prosensing.com  said, it could be an issue with vivado tool. 

Regards,

Reshma R 

View solution in original post

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6 Replies
bruce_karaffa
Scholar
Scholar
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Registered: ‎06-21-2017

The Vivado GUI gets this wrong sometimes.  I have a design from 2017.1 that I ported to 2019.1 that always shows red on all of the pins.  It builds and runs just fine.  I can't find any warnings in the logs relating to this.  I have a post about this but I can't search for it right now.  If it doesn't throw a Critical Warning or Error, I figure it's just another color in the spectrum. 

hongh
Moderator
Moderator
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Registered: ‎11-04-2010

Which part are you using? Which PORT's IOSTANDARD is showing invalid and what IOSTARDARD are you using? 

It will be easier to reproduce the issue if you can provide an example design.

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878 Views
Registered: ‎01-22-2015

@reshmaakhil  As Bruce has said, the "I/O Ports" window for some versions of Vivado is showing IOSTANDARD values in red even though they are correct. This appears to be a bug.

@hongh  For me, this bugs seems to happen ALL THE TIME in Vivado v2019.2 and almost NEVER in Vivado v2018.3.  This bug has been reported several times as shown in the following thread.  However, I have not yet seen Xilinx acknowledge this bug nor file a CR to fix the bug.  I hope you can help.

https://forums.xilinx.com/t5/Implementation/Red-words-at-I-O-Std-settings/m-p/1111254#M28171

 

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reshmaakhil
Explorer
Explorer
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Registered: ‎12-05-2016

 

Hi @hongh ,

I am using Zynq- XC7Z007SCLG225-I.

Code is attached.

All pins are having same issue.

Regards,

Reshma R 

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reshmaakhil
Explorer
Explorer
775 Views
Registered: ‎12-05-2016

 

Hi all,

Even though IOSTANDARD is appearing in red color I am able to generate the bit stream. 

As markg@prosensing.com  said, it could be an issue with vivado tool. 

Regards,

Reshma R 

View solution in original post

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zalfrin
Visitor
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526 Views
Registered: ‎01-08-2020

FWIW, I've seen this with ultrascale+ for LVDS signals.

xczu7eg-fbvb900

set_property IOSTANDARD LVDS [get_ports -of_objects [get_iobanks -regexp 64|66]];

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