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Observer rohini.patil
Observer
7,871 Views
Registered: ‎09-27-2010

ISE 12.1 fails with map error

Hello All,

 

In mapping I am getting error as

 

ERROR:Pack:2604 - The register
   Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_
   phy_if_0/u_phy_ctl_io/gen_addr[9].u_ff_addr has the property IOB=FORCE, but
   was not packed into the output side of an I/O component. The output register
   symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_phy_if_0/u_phy_ctl_io/gen_addr[9].u_ff_addr" has loads outside the I/O
   component.
   The output register symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc
   _phy_if_0/u_phy_ctl_io/gen_addr[9].u_ff_addr" has loads outside the I/O
   component.
ERROR:Pack:2604 - The register
   Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_
   phy_if_0/u_phy_ctl_io/gen_ba[0].u_ff_ba has the property IOB=FORCE, but was
   not packed into the output side of an I/O component. The output register
   symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_phy_if_0/u_phy_ctl_io/gen_ba[0].u_ff_ba" has loads outside the I/O
   component.
   The output register symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc
   _phy_if_0/u_phy_ctl_io/gen_ba[0].u_ff_ba" has loads outside the I/O
   component.
ERROR:Pack:2604 - The register
   Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_
   phy_if_0/u_phy_ctl_io/gen_ba[1].u_ff_ba has the property IOB=FORCE, but was
   not packed into the output side of an I/O component. The output register
   symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_phy_if_0/u_phy_ctl_io/gen_ba[1].u_ff_ba" has loads outside the I/O
   component.
   The output register symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc
   _phy_if_0/u_phy_ctl_io/gen_ba[1].u_ff_ba" has loads outside the I/O
   component.
ERROR:Pack:2604 - The register
   Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_
   phy_if_0/u_phy_ctl_io/gen_cs_n[0].u_ff_cs_n has the property IOB=FORCE, but
   was not packed into the output side of an I/O component. The output register
   symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_phy_if_0/u_phy_ctl_io/gen_cs_n[0].u_ff_cs_n" has loads outside the I/O
   component.
   The output register symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc
   _phy_if_0/u_phy_ctl_io/gen_cs_n[0].u_ff_cs_n" has loads outside the I/O
   component.
ERROR:Pack:2604 - The register
   Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_
   phy_if_0/u_phy_ctl_io/u_ff_we_n has the property IOB=FORCE, but was not
   packed into the output side of an I/O component. The output register symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc_phy_if_0/u_phy_ctl_io/u_ff_we_n" has loads outside the I/O component.
   The output register symbol
   "Inst_system/SDR_SDRAM_CUSTOM/SDR_SDRAM_CUSTOM/mpmc_core_0/gen_sdram_phy.mpmc
   _phy_if_0/u_phy_ctl_io/u_ff_we_n" has loads outside the I/O component.

 

 

and some more similar to this.

Can anyone help me?

Is there any constraint that needed to be given in the UCF?

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6 Replies
Xilinx Employee
Xilinx Employee
7,864 Views
Registered: ‎07-01-2008

Re: ISE 12.1 fails with map error

You need to either remove the IOB=FORCE constraints from the FFs or remove the internal fanout which makes them ineligible for an IOB pack.

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Instructor
Instructor
7,857 Views
Registered: ‎08-14-2007

Re: ISE 12.1 fails with map error

It looks like you wrote some code of your own to do an SDR SDRAM interface?

Some tips:

 

If you code with VHDL and you need feedback from a register that goes to a pin,

DON'T make it an INOUT or BUFFER port.  Make it an output and use an internal

register signal for the feedback.  This will allow the tools to replicate the register

(one for the feedback, one for the IOB) rather than forcing feedback from the pin

or use of a single register driving both OBUF and internal loads.  Make sure

you enable register duplication to allow the register to be packed into the IOB.

 

Same goes for Verilog, use an output port, not an inout.  You don't need to define

an internal variable in Verilog for feedback, however.

 

If you think there should not be this problem (don't see where the internal loads are),

you can change the "FORCE" to "TRUE" to demote these errors to warnings.  Then

you can look at the technology schematic or open the design in FPGA editor to

see where these signals go.

 

HTH,

Gabor

-- Gabor
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Observer rohini.patil
Observer
7,841 Views
Registered: ‎09-27-2010

Re: ISE 12.1 fails with map error

Thanks

Giving the constraint IBO = TRUE fro all these nets solved my problem

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Instructor
Instructor
7,826 Views
Registered: ‎08-14-2007

Re: ISE 12.1 fails with map error

 


@rohini.patil wrote:

Thanks

Giving the constraint IBO = TRUE fro all these nets solved my problem


 

Did it?  Are your flip-flops now pushed into the IOB's?  Or did it just remove the

errors, but you still have to deal with sub-optimal timing in the results?

-- Gabor
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Highlighted
Visitor ginagrec
Visitor
7,261 Views
Registered: ‎04-02-2012

Re: ISE 12.1 fails with map error

Hi,

I too am seeing the same error. Where do we give the IOB = TRUE constraint? In the ucf?

Thx,

Gaurang

Tags (1)
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Xilinx Employee
Xilinx Employee
7,240 Views
Registered: ‎02-11-2010

Re: ISE 12.1 fails with map error

Xilinx constraints guide should show you how to apply this.

 

Here's the link to 13.4 version of this doc:

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/cgd.pdf

 

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