11-06-2020 09:27 PM
I want to calculate the exact delay of a digital circuit at the gate level using Xilinx simulation, therefore, I need to simulate the circuit without optimization. For example, the RTL schematic of the given circuit is
The RTL schematic provides a similar circuit as we wanted to implement using Verilog coding. The aim is to synthesize the above circuit with two MUX and four basic gates without optimizing it into LUT. However, the Technology Schematic is providing a single LUT that implements the truth table of the circuit without considering the intermediate digital blocks.
The delay is 5.753ns for the above circuit which is provided for the Technology schematic of the circuit with basic gates only inside the LUT3.
Is there any command (like KEEP or DONT TOUCH) that can stop the optimization of a digital circuit into LUT in Xilinx simulation, such that the delay can be calculated for the actual circuit as shown in the RTL schematic?
11-07-2020 10:23 AM
my guess is Xilinx uses LUTs because it faster and maybe easier to implement. i am a beginner but i did figure out how to get the HLS to do what i want. my impression is that a serious amount of work and thought went into HLS and Vivado in order to optimize your design. what difference does it make as long as your design fits in the chosen fpga and meets the timing requirements?
11-07-2020 11:38 PM
@Rmccarty Thank you for replying. My main aim is to design an asynchronous digital circuit which can send an acknowledge signal as soon as the computation is done, without waiting for the worst-case delay required by synchronous circuits. That's why I need to examine the delay of the circuit without optimizing it.