07-10-2021 04:06 AM - edited 07-12-2021 04:25 AM
I have singled out the code modification that leads to routing error.
I removed the main_state signal because as a signal within the high-speed clock (ck) domain, it is not supposed to be interfering with low-speed clock (clk) domain stuff, and would only work with Micron simulation where it only uses a single clock domain (since there is no serdes in micron simulation).
However, it is this code modification on removal of "main_state" variable that leads to routing error, because upon variable removal, this IODELAY primitive is now no longer unconnected and have to be placed and routed.
Starting Router ERROR:Route:471 - This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed: Unrouteable Net:ddr3_control/delayed_dqs_r Routing Conflict 1: Net:ddr3_control/ck_270 on pin CLK1 on location OLOGIC_X0Y15 Net:ddr3_control/ck_180 on pin IOCLK1 on location IODELAY_X0Y15 Conflict detected on wire: PINFEED1(-64742,-66654) Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 2 secs
how to use FPGA editor to investigate this routing issue ?
Note: I had also attached a zip file containing the whole ISE project inside this thread.
07-12-2021 04:25 AM
The following code modification for iodelay_dqs_r helps to eliminate the routing conflict between ck_180 and ck_270.
However, delayed_dqs_r is still unrouteable as shown below.
Note: delayed_dqs_r is output from IDELAY primitive and goes to internal FPGA fabric, is this allowed ?
ERROR:Route:471 - This design is unrouteable. Router will not continue. To evaluate the problem please use fpga_editor. The nets listed below can not be routed: Unrouteable Net:ddr3_control/delayed_dqs_r Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 2 secs
[phung@archlinux DDR]$ git diff ddr3_memory_controller.v diff --git a/ddr3_memory_controller.v b/ddr3_memory_controller.v index 0ecfa39..0aa5c47 100644 --- a/ddr3_memory_controller.v +++ b/ddr3_memory_controller.v @@ -951,8 +951,8 @@ reg MPR_ENABLE, MPR_Read_had_finished; // for use within MR3 finite state machi .ODATAIN (1'b0), // data from OLOGIC/OSERDES2 .DATAOUT (delayed_dqs_r), // Output data 1 to ILOGIC/ISERDES2 .DATAOUT2 (), // Output data 2 to ILOGIC/ISERDES2 - .IOCLK0 (ck), // High speed clock for calibration - .IOCLK1 (ck_180), // High speed clock for calibration + .IOCLK0 (ck_90), // High speed clock for calibration + .IOCLK1 (ck_270), // High speed clock for calibration .CLK (clk), // Fabric clock (GCLK) for control signals .CAL (idelay_cal_dqs_r), // Calibrate control signal .INC (idelay_inc_dqs_r), // Increment counter [phung@archlinux DDR]$
07-13-2021 08:42 PM - edited 07-13-2021 08:42 PM
The routing error for delayed_dqs_r could be eliminated by connecting it to DATAOUT2 port instead of DATAOUT port.
But I still have the following routing warnings which caused the routing process to end prematurely:
Then, I changed MAP's "-global_opt" setting from OFF to SPEED, then those routing warnings reduces to only the following:
Note: clk_BUFGP seems to be related to the IODELAY Clock input
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: clk_BUFGP pin: ddr3_control/dq_io.iodelay_dq_r/CLK Unroutable signal: clk_BUFGP pin: ddr3_control/iodelay_dqs_r/CLK Unroutable signal: clk_BUFGP pin: ddr3_control/dq_io.iodelay_dq_r/CLK Unroutable signal: clk_BUFGP pin: ddr3_control/dq_io.iodelay_dq_r/CLK