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Adventurer
Adventurer
1,391 Views
Registered: ‎12-02-2016

Implemantation Area optimization

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Hello,

I am trying to generate a bitstream file for the design, but having the following error during implementation.

 

[Place 30-640] Place Check : This design requires more Slice LUTs cells than are available in the target device. This design requires 53564 of such cell types but only 53200 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device. Please set tcl parameter "drc.disableLUTOverUtilError" to 1 to change this error to warning.

[Place 30-99] Placer failed with error: 'Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.

[Common 17-69] Command failed: Placer could not place all instances

Looks like the design is overflowing, I have tried as much as possible to reduce resources and It got down to 103.58%.

 

Can anyone suggest me some ways to overcome this issue, utilization report is attached for more information.

 

Appreciate your help!

 

Best Regards

 

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Moderator
Moderator
1,279 Views
Registered: ‎06-24-2015

Re: Implemantation Area optimization

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@vatsal.naik

 

Check page 55 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf on details on using the RAM_STYLE attribute.

 

Changing coding style will also help in inferring Block RAM instead of Distributed RAM. Refer page 110 RAM HDL Coding Guidelines for examples.

Thanks,
Nupur
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4 Replies
Moderator
Moderator
1,388 Views
Registered: ‎11-04-2010

Re: Implemantation Area optimization

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1. Synth_design : Try Flow_AreaOptimized_high strategy

2. Look for the chance to replace some large DRAM to BRAM.

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Adventurer
Adventurer
1,368 Views
Registered: ‎12-02-2016

Re: Implemantation Area optimization

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1. The report is generated from Flow_AreaOptimized_high.
2. Can you please point out a bit more, Where to do this change.

Thanks!
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Moderator
Moderator
1,358 Views
Registered: ‎11-04-2010

Re: Implemantation Area optimization

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In your design, too much LUT resource is used(Logic LUT + LUT for RAM). Since you have used the Area optimization strategy for synthesis, then there is little margin for tool to reduce the logic further.

It's hard to convert Logic LUT directly to other logic. 

To reduce the LUT for RAM, you can check your design: Where does the LUT for RAM(DRAM) come from? 

You instantiate DRAM or tool infer DRAM?  

If you instantiate DRAM, you can pick some larger ones to re-instantiate BRAM for them.

If tool infers DRAM, you can try to pick some larger ones and add ram_style attribute to make them use BRAM resource.

 

Yes, it's not easy to achieve the LUT target. If you fails to compress the logic, you have to consider to remove some of your fucntion.

 

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Moderator
Moderator
1,280 Views
Registered: ‎06-24-2015

Re: Implemantation Area optimization

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@vatsal.naik

 

Check page 55 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug901-vivado-synthesis.pdf on details on using the RAM_STYLE attribute.

 

Changing coding style will also help in inferring Block RAM instead of Distributed RAM. Refer page 110 RAM HDL Coding Guidelines for examples.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).

View solution in original post