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Visitor m.valeyrie
Visitor
1,655 Views
Registered: ‎01-03-2018

Implementation Complete but many unroute nets

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Hi every one,

 

I'm facing something new. I previously correctly implemented my design without any problem. For some day, in every design I try to re run implementation without any changement, there is many nets unrouted.

 

I tried many configuration to run implementation, I change my design, without any success.

I attache you synthesized schematic, which is good, and implemented schematic.

 

If you have any idea, I'm very interested.

 

Note that differential pins have always been constrained to the same physical pins (to FMC) and should go straight to SelectIO IP correctly configure to accept LVDS.

I'm using Vivado 2017.4, targetting zedboard.

 

 I thank you in advancefor your help guys.

 

vivado_synth_k.png
vivado_impl_k.png
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1 Solution

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Moderator
Moderator
2,266 Views
Registered: ‎01-16-2013

Re: Implementation Complete but many unroute nets

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@m.valeyrie,

 

I see the following warning during sweep stage of opt_design:


Phase 3 Sweep
WARNING: [Opt 31-163] Instance falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_slave with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_slave with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_slave with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
Phase 3 Sweep | Checksum: 1f95010f3

 

Applying DONT_TOUCH attribute helped to retaining the cells and the design was successfully routed.

set_property DONT_TOUCH 1 [get_cells {falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_slave}]
set_property DONT_TOUCH 1 [get_cells {falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_slave}]
set_property DONT_TOUCH 1 [get_cells {falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_slave}]

 

However, Now I got the following error during bitstream generation:

ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_master: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_slave: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_master: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_slave: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_master: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_slave: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.

 

Upon checking the connection, found that the CLK and CLKB pins of ISERDES are connected GND. Please fix this.

Capture.JPG

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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6 Replies
Xilinx Employee
Xilinx Employee
1,594 Views
Registered: ‎05-08-2012

Re: Implementation Complete but many unroute nets

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Hi @m.valeyrie. Is the output of the report_route_status available? Knowing the pin-to-pin connectivity would help.

 

Also, from the placed design (not routed yet), can the individual net be routed? Below is an example of the command:

 

route_design -nets [get_nets <net_that_has_routing_errors>]

 

 

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Moderator
Moderator
1,586 Views
Registered: ‎01-16-2013

Re: Implementation Complete but many unroute nets

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@m.valeyrie,

 

Can you please share runme.log file present in <project>/<project>.runs/impl_1 folder? If possible, also share the post synthesized design checkpoint file (.dcp). 

 

Open the synthezied design and run the following command to generate post synth dcp file:

write_checkpoint ./post_synth.dcp

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Visitor m.valeyrie
Visitor
1,558 Views
Registered: ‎01-03-2018

Re: Implementation Complete but many unroute nets

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Hi @syedz,

 

Thanks for your reply.

Please find in attachement  runme.log and checkpoint file.

 

Maxime

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Visitor m.valeyrie
Visitor
1,556 Views
Registered: ‎01-03-2018

Re: Implementation Complete but many unroute nets

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Hi @marcb,

 

Thanks for your answer.

 

Here is the report_route_status:

 

Design Route Status
                                                              :      # nets :
-------------------------------------------        : ----------- :
# of logical nets..........................       :        1961 :
# of nets not needing routing.......... :        1212 :
# of internally routed nets........         :        1212 :
# of routable nets.....................          :         749 :
# of fully routed nets.............             :         749 :
# of nets with routing errors..........    :           0 :
 -------------------------------------------         : ----------- :

 

When I run route_design -nets [get_nets <net_that_has_routing_errors>] comand, I get:

 

route_design -nets [get_nets <ch_a_n[0]>]
WARNING: [Vivado 12-507] No nets matched '<ch_a_n[0]>'.
Command: route_design -nets [get_nets {<ch_a_n[0]>}]
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 4 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Empty tcl collection of nets.
INFO: [Common 17-83] Releasing license: Implementation
8 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully

 

Is this a licence problem ?

 

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Moderator
Moderator
2,267 Views
Registered: ‎01-16-2013

Re: Implementation Complete but many unroute nets

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@m.valeyrie,

 

I see the following warning during sweep stage of opt_design:


Phase 3 Sweep
WARNING: [Opt 31-163] Instance falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_slave with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_slave with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
WARNING: [Opt 31-163] Instance falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_slave with type ISERDESE2 and SERDES_MODE=SLAVE will be removed because its outputs are unobservable. If the associated master SERDES requires the slave and is not removed, an error will be issued when generating the bitstream. To avoid this message and the removal of the slave SERDES (assuming it is needed by the master), please add a DONT_TOUCH property to it before running opt_design.
Phase 3 Sweep | Checksum: 1f95010f3

 

Applying DONT_TOUCH attribute helped to retaining the cells and the design was successfully routed.

set_property DONT_TOUCH 1 [get_cells {falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_slave}]
set_property DONT_TOUCH 1 [get_cells {falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_slave}]
set_property DONT_TOUCH 1 [get_cells {falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_slave}]

 

However, Now I got the following error during bitstream generation:

ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_master: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_0/inst/pins[0].iserdese2_slave: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_master: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_1/inst/pins[0].iserdese2_slave: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_master: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.
ERROR: [DRC REQP-105] enum_DATA_RATE_DDR_connects_CLK_ACTIVE_connects_CLKB_ACTIVE: falcon_design_3_wrapper_inst/falcon_design_3_i/selectio_wiz_2/inst/pins[0].iserdese2_slave: The use of attribute DATA_RATE set DDR requires connectivity for the CLK and CLKB input pins.

 

Upon checking the connection, found that the CLK and CLKB pins of ISERDES are connected GND. Please fix this.

Capture.JPG

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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Visitor m.valeyrie
Visitor
1,524 Views
Registered: ‎01-03-2018

Re: Implementation Complete but many unroute nets

Jump to solution

Hi @syedz,

 

Thanks for these informations.

 

I applyed "DONT_TOUCH" command and nets are fully routed. I found a new timing problem then I can't see the error in bitstream generation for now. I'm working on it, then please considere my problem solved.

 

Thank you :)

 

Maxime

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