10-22-2019 07:56 PM
Dear Xilinx Team,
I have been having the instantiating a Block rom within my custom ip and read its contents trough the ZynQ process..
My design is as follows (fig1)
BROM customip created an AXI peripheral using IP CORE is designed to accept the address from the ZYNQ and present the user the contents of the ROM.. The custom ip get synthesized correctly, I have added the .xci, netlist and the memory initialization files too.
The problem starts when I connect it with the ZYNQ module, at the implementation stage, I get the following errors. (fig2)
I would appreciate some help in this regard.
Note : I have tried implementing an adder created using IP CORE, this works.
10-22-2019 10:04 PM
Hi @jalex ,
The issue might be because of mismatch between the name of your IPs as they have been added to the project and the name you are using to instantiate them to your project.
Basically, when you add an IP to you project, you select an name which is not necessarily the "catalog name of the IP". By default, it is not. Vivado add an index to the name. This way you could add multiple time the same IP but with different configurations.
If you modify your top level file, your issue will be solved.
Hope this helps.
10-23-2019 10:39 PM
Thank you for the reply, the only difference in the name of the custom IP is an addition of [-0], When added the IP, the design shows it as BROM_Customip_0 but in HDL wrapper it is defined as "design_1_BROM_Customip_0_0", where deisgn1.VHD is the VHDL code developed from VIVADO wrapper design_1_wrapper.vhd is the TOP module. All these files are "read-only", so how do I change? Even when I don't allow VIvado to develop the wrapper, only the top module [design_1_wrapper.vhd]is available for edit, others are still in "read-only".
When I check the BROM IP that I have added within my custom logic, the difference in names is "blk_mem_gen_0" and one that wrapper developed is "xil_defaultlib.blk_mem_gen_0".. Now again the VHDL code developed is read-only, so how to solve this issue. I have shared my code so that you could help me with a solution.
Please note. I didn't have problems when I did the same with an adder IP taken directly from the Xilinx repository. This problem happens with Block RAM
Due to space constraints, I have uploaded my files to the following link
Appreciate if you could point out my mistake
10-26-2019 05:25 PM
11-06-2019 02:30 AM
Hi @jalex ,
I was working on your design and found that the sub IP blk_gen_mem_0 was mising in source window when tried to open the BROM_Customip_v1_0 IP in IP packager. After adding the xci file and generating output products i tried to synthesis the design but it failed with error:
[Ipptcl 7-519] NULL COE Data pointer: Unable to open the file
I am further working on that issue with our IP team. will update shortly.
11-06-2019 03:41 AM
Thank you. I believe I have sent all the required files. I have also sent across the core idea of my design. Its just trying to use BROM/RAM/FIFo ipcore within a user defined vdhl code. Later convert the user defined code as a user defined ip and add it to the zynq environment. Later control it from SDK. The whole idea worked with an adder ip but failed when used BROM/FifO.
I hope i have clearly explained the problem. Appreciate your team can prrovide me the solution
11-06-2019 05:40 AM
Hi @jalex ,
Your Custom IP is packaged with a missing IP, which is why you are seeing the missing file in the hierarchy.
Open BD -> Right Click the IP -> Select Edit in IP packager -> a new project will be opened for editing the IP -> in this project go to IP catalog and add block memory generator IP to the project by customizing the IP as per your use case -> then try Synthesis and Implementation in this project if done then -> merge changes from the wizard and re-package the IP -> if there are any errors in this project the fix them and then repackage the IP.
Once re-packaged -> close this project -> go to main project -> upgrade IP -> Run synthesis and Implementation.
I have tried this at my end and I was able to perform Synthesis and Implementation in the main project after doing the above steps.
11-06-2019 08:42 PM
Thank you for the reply, yes I was able to solve the problem. I didn't realize that the ipcore was missing when I packaged the IP, but I am baffled that this problem didnt happen when I used the Adder IP. (the same problem persisted when FIFO IP was used too). Is there something that I need to take care when packaging RAM-based IPs?
Once Again thank you
11-06-2019 10:19 PM - edited 11-06-2019 10:19 PM
In the process of packaging a custom IP ( even if it is RAM-based ), there is no need for special care to be taken.
We just need to make sure that the project ( which is later to be packaged as an IP ) does not have any errors or warnings of concern,
i.e. we should check whether the project is synthesized and Implemented as expected before packaging it as a Custom IP.