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rothenbergt
Visitor
Visitor
10,256 Views
Registered: ‎09-01-2018

Implementation Fails with error [Place 30-494] The design is empty and [Common 17-69]

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[Place 30-494] The design is empty
Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.

 

[Common 17-69] Command failed: Placer could not place all instances

I am trying to simulate this design to synthesize and implement the design on the FPGA BASYS 3 board. 

 

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 09/01/2018 07:35:04 PM
// Design Name: 
// Module Name: Part_1_Sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Part_1_Sim(
    );
  
    reg Inp_1_t;
    reg Inp_2_t;
    
    wire Outp_t;
    
      Part_1 UUT (
      .Inp_1 (Inp_1_t),
      .Inp_2 (Inp_2_t),
      .Outp(Outp_t)
      );
      initial begin
      Inp_1_t = 1'b0;
      Inp_2_t = 1'b0;
      
      end
  
    always #10 Inp_1_t = ~Inp_1_t;
    always #20 Inp_2_t = ~Inp_2_t;
endmodule
set_property PACKAGE_PIN V17 [get_ports Inp_1]
set_property PACKAGE_PIN V16 [get_ports Inp_2]
set_property PACKAGE_PIN U16 [get_ports Outp]
set_property IOSTANDARD LVCMOS33 [get_ports Inp_1]
set_property IOSTANDARD LVCMOS33 [get_ports Inp_2]
set_property IOSTANDARD LVCMOS33 [get_ports Outp]

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 09/01/2018 07:16:12 PM
// Design Name: 
// Module Name: Part_1
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Part_1(
    input Inp_1,
    input Inp_2,
    output Outp
    );
    assign Outp = Inp_1 & Inp_2;
endmodule
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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
10,222 Views
Registered: ‎01-16-2013

@rothenbergt

 

I am sure that you are synthesizing/implementing the test bench file which is "Part_1_Sim". Since this is a test bench file, you should not implement this module and use it only for Simulation. 

 

Select "Part_1_Sim" file and under properties window uncheck synthesis and Implementation and check only Simulation as shown in below figure: 

Capture.JPG

 

Now reset and rerun the complete vivado flow which should pass successfully. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

7 Replies
hemangd
Moderator
Moderator
10,232 Views
Registered: ‎03-16-2017

Hi @rothenbergt,

 

Tried your testcase on Vivado 2018.2 with virtex 7 board and i am not facing any errors while implementation. 

 

Regards,

hemangd

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
hemangd
Moderator
Moderator
10,231 Views
Registered: ‎03-16-2017

Hi @rothenbergt,

 

Tried your testcase on Vivado 2018.2 with virtex 7 board and i am not facing any errors while implementation. 

 

Regards,

hemangd

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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syedz
Moderator
Moderator
10,223 Views
Registered: ‎01-16-2013

@rothenbergt

 

I am sure that you are synthesizing/implementing the test bench file which is "Part_1_Sim". Since this is a test bench file, you should not implement this module and use it only for Simulation. 

 

Select "Part_1_Sim" file and under properties window uncheck synthesis and Implementation and check only Simulation as shown in below figure: 

Capture.JPG

 

Now reset and rerun the complete vivado flow which should pass successfully. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

rothenbergt
Visitor
Visitor
10,205 Views
Registered: ‎09-01-2018

Amazing! Thank you so much Syedz!

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9,454 Views
Registered: ‎12-27-2018
I tried your solution and now when I synthesize the file, it says "There are no HDL sources in file set 'sources_1'. Please use the Add Sources command". Can you help me?
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syedz
Moderator
Moderator
9,350 Views
Registered: ‎01-16-2013

@normal_engineer

 

Please create a new forum thread if you have a query. Check in the sources hierarchy if you have any HDL file and correct hierarchy. 

If this is Block design then you need to create a wrapper around the BD file. Right click on BD file and select create wrapper

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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MetzgerM
Newbie
Newbie
650 Views
Registered: ‎04-06-2021

I had the same issue. So SIMPLE when you know what you're doing!! Thanks!

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