cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
alew_wouter
Observer
Observer
1,079 Views
Registered: ‎06-03-2020

Implementation Unroutable Placement

I work on Artix-7 and I have the following error when Place Design :

 

[Place 30-764] Unroutable Placement! RAMBs driven by regional clock buffers (BUFRs and BUFHs) need to be in the same clock region as the buffers. There are not enough free RAMB sites available in the clock region where some of the buffers are placed. Some of them are listed below.
DIV_8_INSTANCE/BUFR_DIV2_INSTANCE (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y8
DIV_8_INSTANCE/BUFR_DIV4_INSTANCE (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y9
BUFR1_INSTANCE (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y4
BUFR2_INSTANCE (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y5
CLK_WIZARD_INSTANCE/inst/clkout1_buf_en (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X0Y12
CLK_WIZARD_INSTANCE/inst/clkout2_buf_en (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X0Y13
CLK_WIZARD_INSTANCE/inst/clkout3_buf_en (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X0Y14
CLK_WIZARD_INSTANCE/inst/clkout4_buf_en (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X0Y15

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

 

Clock Rule: rule_bufio_clklds
Status: PASS
Rule Description: A BUFIO driving any number of IOBs must be placed within the same bank. In V7, there
is at most one IO bank in each clock region so the SameClockRegion rule is sufficient to satisfy the
requirement.
BUFIO_INSTANCE_DCLK (BUFIO.O) is locked to BUFIO_X0Y7
LVDS_DESERIALIZATION_INSTANCE/ISERDESE2_INSTANCE_FCLK (ISERDESE2.CLK) is locked to ILOGIC_X0Y54
LVDS_DESERIALIZATION_INSTANCE/ISERDESE2_INSTANCE_SDIN (ISERDESE2.CLK) is locked to ILOGIC_X0Y52

Clock Rule: rule_iotile_bufr
Status: PASS
Rule Description: An IO driving a BUFR must both be placed in the same clock region
IBUFDS_DCLK_INSTANCE (IBUFDS.O) is locked to IOB_X0Y78
BUFR1_INSTANCE (BUFR.I) is provisionally placed by clockplacer on BUFR_X0Y4

Clock Rule: rule_bufr_IoClkLds
Status: PASS
Rule Description: A BUFR driving any number of IOBs must be placed within the same clock region
BUFR1_INSTANCE (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y4
LVDS_DESERIALIZATION_INSTANCE/ISERDESE2_INSTANCE_FCLK (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y54
LVDS_DESERIALIZATION_INSTANCE/ISERDESE2_INSTANCE_SDIN (ISERDESE2.CLKDIV) is locked to ILOGIC_X0Y52
IDELAYE2_SDIN_INSTANCE (IDELAYE2.C) is locked to IDELAY_X0Y52

Clock Rule: rule_clk_locked_loads
Status: PASS
Rule Description NOT AVAILABLE
BUFR1_INSTANCE (BUFR.O) is provisionally placed by clockplacer on BUFR_X0Y4
IDELAYE2_SDIN_INSTANCE (IDELAYE2.C) is locked to IDELAY_X0Y52

Clock Rule: rule_gclkio_mmcm_1load
Status: PASS
Rule Description: An IOB driving a single MMCM must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
is NOT set
CLK_WIZARD_INSTANCE/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y76
CLK_WIZARD_INSTANCE/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
CLK_WIZARD_INSTANCE/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
CLK_WIZARD_INSTANCE/inst/clkout1_buf (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y16

Clock Rule: rule_mmcm_bufhce
Status: PASS
Rule Description: An MMCM driving a BUFH must both be in the same horizontal row (clockregion-wise)
CLK_WIZARD_INSTANCE/inst/mmcm_adv_inst (MMCME2_ADV.CLKOUT0) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
CLK_WIZARD_INSTANCE/inst/clkout1_buf_en (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X0Y12

Clock Rule: rule_mmcm_mmcm
Status: PASS
Rule Description: An MMCM driving an MMCM must be in the same CMT column, and they are adjacent to
each other (vertically), if the CLOCK_DEDICATED_ROUTE=BACKBONE constraint is NOT set
CLK_WIZARD_INSTANCE/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
and CLK_WIZARD_INSTANCE/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBIN) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

 

Artix 7-Series FPGAs have only 4 clock regions, X0Y1, X1Y1, X0Y2, X1Y2.  How can i have Y4 or Y52 ?

 

Thanks

Tags (3)
0 Kudos
6 Replies
1,033 Views
Registered: ‎01-22-2015

@alew_wouter 

It seems you are using BUFR to send clock to RAMB. The clock output of BUFR can only reach RAMB found in the clocking region that contains the BUFR.  The error indicates that no more RAMB are available in the clocking region that contains BUFR.

One solution could be to use BUFMR to drive two or three BUFR in parallel as shown in Fig 2-25 of UG472(v1.14).  Then, RAMB in multiple clock regions can be used.

Another solution could be to use BUFG instead of BUFR. Then, the clock output of BUFG can reach all RAMB in the FPGA.

If these solutions don’t work for you then tell us why you are using BUFR.

Cheers, Mark

0 Kudos
alew_wouter
Observer
Observer
1,005 Views
Registered: ‎06-03-2020

Thanks for these proposals.

 

I remove the two BUFR of DIV_8 instance but the issue is still here.

 

I use the other BUFRs (BUFR1/BUFR2) to drive ISERDESE2 to de-serialize LVDS data. I use the output of the second BUFR as a write clock for a large FIFO to store data before a compute.

For this purpose I think I can't use BUFG because of timing issue.

If use BUFMR to drive another BUFR in other clock domain, is the first BUFR and BUFIO (for drive CLK and CLKB) for ISERDESE2 will be in different clock domain ? Is it an issue ?

 

A question remain, for example, what do the values BUFR_X0Y8 means if clock domain X0Y8 does not exist ?

 

0 Kudos
975 Views
Registered: ‎01-22-2015

@alew_wouter 

Use of BUFMR to drive multiple BUFIO and multiple BUFR is also described by Fig A-6 in UG472. Be sure to do the BUFR alignment described on page 110.  Then, Vivado will clearly understand the relationship between all BUFR output clocks in Fig A-6 and will tell you if there is a problem crossing data between these different clock domains.

Another option is to drive CLK and CLKDIV inputs of ISERDES with an MMCM and BUFGs (instead of with BUFIO and BUFR). This is described on page 153 of UG471(v1.10). This will make it easy to reach RAMB in other clocking regions but timing for ISERDES may suffer.

Finally, BUFR_Y0X8, is an identifier for a specific BUFR.  That is, the _Y0X8 is not referring to a specific clocking region.

.

893 Views
Registered: ‎01-22-2015

@alew_wouter 

Avrum and I believe that the BUFR Alignment procedure described on pg110 of UG472(v1.14) is incorrect.  Please see the following post for details.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Multiple-region-BUFR-alignment/m-p/1062626 

0 Kudos
alew_wouter
Observer
Observer
872 Views
Registered: ‎06-03-2020

markg@prosensing.com 

 

I use BUFMR to drive multiple BUFRs. One clock domain for ISERDESE2 (blue) and another one for the write clock of the FIFO (red). I use the following LOC properties :

set_property LOC BUFMRCE_X0Y2 [get_cells BUFMRCE_INSTANCE]
set_property LOC BUFIO_X0Y7 [get_cells BUFIO_INSTANCE_DCLK]
set_property LOC BUFR_X0Y4 [get_cells BUFR1_INSTANCE]
set_property LOC BUFR_X0Y5 [get_cells BUFR2_INSTANCE]

set_property LOC BUFR_X0Y3 [get_cells BUFR1_B_INSTANCE]
set_property LOC BUFR_X0Y2 [get_cells BUFR2_B_INSTANCE]

 

Sans titre.png

 

 

The result is the same, no more RAMB are available in the clocking region that contains the BUFR. I think RAMB in multiple clock regions can not be used after a BUFR.

 

When I use BUFG for the FIFO write clock, implementation works. The FIFO use several clock domains.

Use BUFG (orange) after BUFR is not recommanded for 7-Series and it does not work when I test with ILA but implementation not fails. 

The option of drive CLK and CLKDIV inputs of SERDES with an MMCM and BUFGs seems to be the unique solution.

 

Otherwise, thanks for the BUFR Alignment solution. 

0 Kudos
819 Views
Registered: ‎01-22-2015

I think RAMB in multiple clock regions can not be used after a BUFR.

You are correct.  BUFR can drive a clock to a large Block-RAM only if all the RAMB blocks used to build the Block-RAM can be placed in the same clocking region as the BUFR.

0 Kudos