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gdoraisa
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Registered: ‎06-23-2021

Implementation error message on set property

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After implementation, the Vivado log file shows a critical warning.

[Common 17-55] 'set_property' expects at least one object. ["myFPGA.xdc":515]

 

In myFPGA.xdc line 515 is

set_property LOC MMCME2_ADV_X0Y2 [get_cells eight_clks_5MMCM/MMCME2_ADV_36_18_9_4_5]

I checked and verified the path is correct and all are upper cases in the source file. There is clock from a port but that clock goes to BUFG and the output goes to this block. The input to the BUFG is constrained. But not sure what the syntax is to constraint the output of BUFG. Also not sure what object it is expecting back?

 

 

 

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hongh
Moderator
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206 Views
Registered: ‎11-04-2010

Please open the implemented design and check MMCM's LOC with the below command in TCL CONSOLE:

get_property LOC  [get_cells eight_clks_5MMCM/MMCME2_ADV_36_18_9_4_5] 

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drjohnsmith
Teacher
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Registered: ‎07-09-2009

not an answer

  but do you need to lock the location of the MMCM ?

        

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gdoraisa
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Registered: ‎06-23-2021

Maybe that is it. However, not sure what the syntax to add in XDC to lock MMCM. What I have are the following two.

set_property BEL MMCME2_ADV [get_cells eight_clks_5MMCM/MMCME2_ADV_36_18_9_4_5]
set_property LOC MMCME2_ADV_X0Y2 [get_cells eight_clks_5MMCM/MMCME2_ADV_36_18_9_4_5]

 

 

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hongh
Moderator
Moderator
207 Views
Registered: ‎11-04-2010

Please open the implemented design and check MMCM's LOC with the below command in TCL CONSOLE:

get_property LOC  [get_cells eight_clks_5MMCM/MMCME2_ADV_36_18_9_4_5] 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post