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Visitor cmmnml
Visitor
14,090 Views
Registered: ‎05-20-2009

Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

Following are the details of my design

 

Target device : Spartan 3E 100 - TQ144 (xs3s100e-4tq144)

ISE version    : 11.1

 

 

Problem :

 

I've been using ISE 10 (service pack 3) for my design and didn't have any problems. With the recent release of ISE 11.1, I moved to the new version and when I tried to build my design using 11.1, I get the following error.

 

 

ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM

site pair. The clock component <u0/DCM_SP_INST> is placed at site <DCM_X0Y0>. The clock IO/DCM site can be paired

if they are placed/locked in the same quadrant. The IO component <clk> is placed at site <P128>. This will not

allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for

this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING

and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very

poor timing results. It is recommended that this error condition be corrected in the design. A list of all the

COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to

override this clock rule.

< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

< PIN "u0/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

 

 

 

In my design the clock input is connected to P128 which is GCLK8. Even though the error indicate P128 and DCM_X0Y0 are at different sites, the device view of PlanAhead indicates those two are physically in close positions. 

 

From one Xilinx answer record (http://www.xilinx.com/support/answers/31462.htm), it appears that this problem was found in ISE 10.1 but fixed in service pack 3. I'm wondering whether the same problem is appeared again in ISE 11.1.

 

 

If any one could provide any thoughts on this, that would be a great help.

 

 

 

Thanks

 

 

 

 

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16 Replies
Historian
Historian
14,081 Views
Registered: ‎02-25-2008

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair


cmmnml wrote:

Following are the details of my design

 

Target device : Spartan 3E 100 - TQ144 (xs3s100e-4tq144)

ISE version    : 11.1

 

 

Problem :

 

I've been using ISE 10 (service pack 3) for my design and didn't have any problems. With the recent release of ISE 11.1, I moved to the new version and when I tried to build my design using 11.1, I get the following error.

 

 

ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM

site pair. The clock component <u0/DCM_SP_INST> is placed at site <DCM_X0Y0>. The clock IO/DCM site can be paired

if they are placed/locked in the same quadrant. The IO component <clk> is placed at site <P128>. This will not

allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for

this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING

and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very

poor timing results. It is recommended that this error condition be corrected in the design. A list of all the

COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to

override this clock rule.

< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

< PIN "u0/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

 

 

 

In my design the clock input is connected to P128 which is GCLK8. Even though the error indicate P128 and DCM_X0Y0 are at different sites, the device view of PlanAhead indicates those two are physically in close positions. 

 

From one Xilinx answer record (http://www.xilinx.com/support/answers/31462.htm), it appears that this problem was found in ISE 10.1 but fixed in service pack 3. I'm wondering whether the same problem is appeared again in ISE 11.1.

 

 

If any one could provide any thoughts on this, that would be a great help.

 

 

 

Thanks

 

 

 

 


You have to carefully look at the diagram of the clock stuff in the data sheet. Each clock input is near particular BUFGs and particular DCMs. Sometimes the tools can't figure out what is best. The easiest thing to do is use the guide in the data sheet to tell  you which BUFGs and DCMs you should use and add that info to your UCF by hand.

 

-a

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
13,951 Views
Registered: ‎11-28-2007

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

You were probably looking at a difference device. I just checked it in FPGA_EDITOR, pin P128 (top side) and DCM_X0Y0 (bottom side) are at oppsite side of  xs3s100e-4tq144.
 Cheers,
Jim

cmmnml wrote:

Following are the details of my design

 

Target device : Spartan 3E 100 - TQ144 (xs3s100e-4tq144)

ISE version    : 11.1

 

 

Problem :

 

I've been using ISE 10 (service pack 3) for my design and didn't have any problems. With the recent release of ISE 11.1, I moved to the new version and when I tried to build my design using 11.1, I get the following error.

 

 

ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM

site pair. The clock component <u0/DCM_SP_INST> is placed at site <DCM_X0Y0>. The clock IO/DCM site can be paired

if they are placed/locked in the same quadrant. The IO component <clk> is placed at site <P128>. This will not

allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for

this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING

and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very

poor timing results. It is recommended that this error condition be corrected in the design. A list of all the

COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to

override this clock rule.

< NET "clk" CLOCK_DEDICATED_ROUTE = FALSE; >

< PIN "u0/DCM_SP_INST.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

 

 

 

In my design the clock input is connected to P128 which is GCLK8. Even though the error indicate P128 and DCM_X0Y0 are at different sites, the device view of PlanAhead indicates those two are physically in close positions. 

Cheers,
Jim
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Contributor
Contributor
13,700 Views
Registered: ‎11-23-2008

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

probably your answer is here;

http://www.xilinx.com/support/answers/21724.htm

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Visitor lukeperkins
Visitor
13,169 Views
Registered: ‎09-16-2007

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

I had a design that compiled on Thursday running 11.1. I made the FOOLISH mistake of upgrading to 11.2. I am now DEAD IN THE WATER! I filed a WebCase #799365 but I have yet to hear a response from Xilinx.

 

Things I have tried:

 

1) Delete ALL meta data files. The ISE thinks too hard and looks at previous work, even when it is corrupt.

2) Added a BUFG for the master clock going to my two DCMs.

3) Reviewing my MAP and PAR settings. 11.2 has different switches than 11.1. This is probably the problem.

 

Anyone? What am I missing.

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Contributor
Contributor
13,111 Views
Registered: ‎11-23-2008

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

10.1 to 11.1 and 11.1 to 11.x version updates have very strong changes about cores and etc.

 

I think, if you can, click "uninstal last update" in start/programs/.... menu. Return prevous version. If you start a project, i think don't do any update. If not, you may couldn't finish it :) :(

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Visitor endi
Visitor
12,575 Views
Registered: ‎11-11-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

Question: 

 

What is the simplest way to find out which BUFGCTRL has a direct fast path to each clock input pin?

 

Background:

 

I've recently bumped into an error using ISE 11.3.  I'm using an XC5VFX70TFF665 on a 3rd-party circuit board that has many clock inputs, one of which is on pin J21, which is named IO_L8P_CC_11.  This pin enters the west side of the die, and all the BUFGCTRL blocks are near the middle, across the PPC440 core which appears to have a limited number of route-overs.

 

I get this error message:

ERROR:Place:645... The clock IOB component rxclk is placed at site <IOB_X0Y183>.  The clock IO site can use the fast path between the IO and the Clock buffer/GCLK if the IOB is placed in the master Clock IOB Site...

 

This error becomes a warning when I add NET "rclk" CLOCK_DEDICATED_ROUTE = FALSE; to the *.ucf, and the inputs that are clocked by J21 have up to -300ps hold slack.

 

When I use Process: Implement Design: Place & Route: View/Edit Routed Design (FPGA Editor), I see that the path to the BUFGCTRL goes through seven switch boxes and does a little backtracking on its way.  I can find an unused BUFGCTRL that is infinitessimally closer to the pin, and when I add INST "sys/hp_0/*.bufg_phy_rx_0" LOC = "BUFGCTRL_X0Y26"; to the UCF it becomes a straighter route that actually meets timing without creating other problems.  But I don't see any obvious relationship between the J21 pin and any of the clock resources.

 

When I look in the Virtex-5 User Guide, and search for "fast path" or "master Clock IOB", I don't find anything.  Likewise when I search the Xilinx website, and find various data sheets and pinout files for the Virtex-5, but no table relating specific pins to specific clock resources.  It should have entries that are clear, like J21 = IO_L8P_CC_11 = BUFGCTRL_X0Y29 or something.  Perhaps this is defined in a document I can't find until I happen across the correct buzzword to search.  But I suspect that there is no fast path from J21, in which case the tool is ineffectively reporting a poor pin choice.

 

I'd like to remove the CLOCK_DEDICATED_ROUTE = FALSE constraint so the path to the BUFGCTRL will not be too long as I make significant incremental design changes.

 

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Historian
Historian
12,565 Views
Registered: ‎02-25-2008

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair


endi wrote:

Question: 

 

What is the simplest way to find out which BUFGCTRL has a direct fast path to each clock input pin?

 

Oddly, the S3 user guide has a nice picture that indicates which GCLK pins directly connect to which BUFCTRLs, but this picture is not in either the V4 or V5 user guides. This is no fun.

----------------------------Yes, I do this for a living.
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Visitor endi
Visitor
12,561 Views
Registered: ‎11-11-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

Thank you for noticing, Bassman.  I also didn't see any description of pin features and how that maps to the pin name.  In other families, global clock pins are usually designated with a GC.  The pin being used is not a GC pin, it is a CC pin.  Since the Virtex-5 may have different clock path options than Spartans and other Virtex devices, I don't want to infer the clock functionality from documentation for the other families.  If indeed there is no Virtex-5 clock pin table to be found, then it might explain why this pin was chosen by my board supplier if it turns out not to have any fast path. 
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Xilinx Employee
Xilinx Employee
12,559 Views
Registered: ‎11-28-2007

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

The Virtex5 packaging UG explains the conventions used in IO names (see snapshot below). Regarding which inputs can drive which global clock buffer (BUFG), only glock clock inputs (GC pins) can drive BUFG and they have to be in the same top or bottom half. For a particular package, you can use ADEPT (http://mysite.verizon.net/jimwu88/adept/) component view to show which glock clock inputs, BUFG/DCM/PLL belong to the same half.Check this blog for more details.

 

 

Cheers,
Jim
ScreenHunter_03 Dec. 14 22.06.gif
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Visitor endi
Visitor
9,555 Views
Registered: ‎11-11-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

The package user guide clearly states to use the P input for single-ended clocks, and explains that some pins that are considered to be in a center column cannot drive BUFRs.  When I run the FPGA editor I do see what appear to be I/O pads in four segments of a columns near X101 on the "RPM grid", so perhaps that is what is meant by center column.

 

The Adept tool does a nice job showing what the center column pins are.  More to the point, it does a good job illustrating the fact that IO pins may be clocked by any CC in the same bank.  But I can still only guess that the CC pins have no fast paths to do anything else.

 

Even if this pin were a GC input, I don't know if the Virtex-5 has a single fast path from a given GC pin to a given BUFGCTLR, or if there is more flexibility.  Perhaps an IOB with Y217 only has a fast path to a BUFGCTRL with Y217. 

 

I can see in the UCF that the designer meant for this pin to drive a BUFGCTRL, and when the LOC constraint is removed, ISE still chooses a BUFGCTRL for some reason.  It may be used to clock internal logic in addition to I/O.  The IP is not open source, so changing it is out of the question.  Simply LOC constraining the clock to a BUFR is unlikely to work.

 

I guess I'm stuck with CLOCK_DEDICATED_ROUTE=FALSE, since there is no way to determine if any fast path to a BUFGCTRL exists, and in the unlikely event there is one, I probably will not be able to find it.

 

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Xilinx Employee
Xilinx Employee
9,550 Views
Registered: ‎11-28-2007

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

First of all, CC is not "Center Column". It stands for "Clock Capable". CC pins have dedicated routes to BUFIO and BUFR (no BUFRs in the center for Virtex5).

 

For GC pin driving BUFGs's, as long as they are in the same half, there is dedicated route between them (see the UG snapshot below). ADEPT does show which GCs and BUFGs are in the same half (see http://myadeptblog.blogspot.com/2009/12/virtex5-component-view.html).

 

 

Cheers,

Jim

 

Cheers,
Jim
ScreenHunter_02 Dec. 15 12.50.gif
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Observer mat01
Observer
9,537 Views
Registered: ‎05-04-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

Hi, I've got the same problem, just opened my Design in 11.4 (! just updated !) and get :

 

ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
   site pair.  The clock component <DCM_inst_8/DCM_SP> is placed at site <DCM_X1Y1>.  The clock IO/DCM site can be
   paired if they are placed/locked in the same quadrant.  The IO component <MAIN_CLK> is placed at site <PAD154>.  This
   will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is
   acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message
   to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may
   lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of
   all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf
   file to override this clock rule.
   < NET "MAIN_CLK" CLOCK_DEDICATED_ROUTE = FALSE; >
   < PIN "DCM_inst_8/DCM_SP.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >

 

the same design runs through 10.1.03 without problem. And the clock source is connected to a "P" pin ! I get thrown out at Xilinx when trying to open a WebCase.

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Highlighted
Visitor endi
Visitor
9,533 Views
Registered: ‎11-11-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

Hello Matt, it appears that 10.1 didn't treat this condition as an error.  I recall setting a number of environment variables to bypass certain errors in 9.2 and 10.1 which had the unfortunate side affect of bypassing every error of the type on every pin of every project.  Bypassing only the paths in question makes a whole lot more sense, especially if 11.X and future ISE versions react to this condition by trying to avoid it in the first place.

 

At least the tool is telling you to locate the IOB and the DCM in the same quadrant, which implies that every clock IOB (of whatever type PAD154 is) has a fast path to every DCM in the same geographical quadrant.

 

Since Xilinx employees do actually check the forums from time to time, it might help to clearly identify your part, including the package type, so the context of the PAD154 makes sense.

 

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Observer mat01
Observer
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Registered: ‎05-04-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

it is a Spartan3A  xc3s200a-4ft256 . Can I manually select the DCM to be used ? If yes, how ?
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Visitor endi
Visitor
9,529 Views
Registered: ‎11-11-2009

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair

Examples of what you need in your constraint file (*.UCF) are

 

INST "*/proj_dcm_standby_mainclk/STANDBY_INST/DCM_ADV_INST" LOC=DCM_ADV_X0Y2;

 

and 

 

INST "toplevel_gcm_0/dcm_base_busclk" LOC=DCM_ADV_X0Y4;

 

which place the Virtex 4 standby and base GCM macros onto particular DCM_ADV resources seen using the "View/Edit Routed Design (FPGA Editor)" tool under the Place and Route processes.  Spartan 3 DCMs will have different names but should be easy to identify.  Discovering the instance name is a bit trickier, since it may bear little resemblence to anything you declared in your design, but the error message can be helpful.  Once you find the name assigned to your instance, then you can clone the name to put into the UCF and then assign the LOC to a DCM that is nearby.  The FPGA editor is helpful when you turn text on and zoom in on a column of DCMs, the unoccupied ones will display their location.

 

 

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Historian
Historian
9,524 Views
Registered: ‎02-25-2008

Re: Implementation error with ISE 11.1 - ERROR:Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM site pair


mat01 wrote:
it is a Spartan3A  xc3s200a-4ft256 . Can I manually select the DCM to be used ? If yes, how ?

Yes, do it in the floorplanner or PACE or whatever it's called now. Also manually select the clock buffers associated with the DCM. Sometimes the tools are too stupid to choose the correct buffers for a given DCM. Read the Spartan 3-family user guide, it has a nice picture that shows what buffers are associated with each DCM and each GCLK pin.

----------------------------Yes, I do this for a living.
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