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Explorer
Explorer
1,573 Views
Registered: ‎01-23-2018

[Implementation error]

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Hi,

 

 

I wanted to know how can I resolve the next issues because I'm new with Vivado and it's the first time I run a design:

 

"[DRC NSTD-1] Unspecified I/O Standard: 1 out of 7 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_rst_n."

 

 

"[DRC UCIO-1] Unconstrained Logical Port: 3 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clk_n, sys_clk_p, and sys_rst_n."

 

 

Regards,

 

 

Joel

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Moderator
Moderator
1,899 Views
Registered: ‎01-16-2013

Re: [Implementation error]

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@joel.sanchez,

 

From the pin planning image, I see the IO location for IO ports mentioned in error message is picked by tool. (WR33 and AR36)

sys_clk_n, sys_clk_p, and sys_rst_n." 

 

You need to define the location in constraint file to overcome the error message. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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5 Replies
Moderator
Moderator
1,570 Views
Registered: ‎05-31-2017

Re: [Implementation error]

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Hi @joel.sanchez,

 

Please check the AR#56354 on how to resolve this error.

Explorer
Explorer
1,545 Views
Registered: ‎01-23-2018

Re: [Implementation error]

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Hi @shameera,

 

 

hope you can help me because maybe I'm wrong. I have solved one of the issues but the other one still being there:

 

"[DRC UCIO-1] Unconstrained Logical Port: 3 out of 7 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clk_n, sys_clk_p, and sys_rst_n."

 

 

I have given a value to the pins as you can see on the first image attached, the second one has the schematic where it can be seen that none of the ports is in GND or invalid space, the second image can be also found on page 290 of the next URL : https://www.xilinx.com/support/documentation/user_guides/ug575-ultrascale-pkg-pinout.pdf

 

 

Hope you can help me, It's the first time I run a bitstream I was always using Simulation.

 

 

Thanks

pins.PNG
schematic.PNG
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Moderator
Moderator
1,900 Views
Registered: ‎01-16-2013

Re: [Implementation error]

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@joel.sanchez,

 

From the pin planning image, I see the IO location for IO ports mentioned in error message is picked by tool. (WR33 and AR36)

sys_clk_n, sys_clk_p, and sys_rst_n." 

 

You need to define the location in constraint file to overcome the error message. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
Explorer
Explorer
1,524 Views
Registered: ‎01-23-2018

Re: [Implementation error]

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Hi @syedz,

 

so I will have to create a .xdc file and put sys_clk_n, sys_clk_p, and sys_rst_n definitions. I only have to add those or pci_exp* too?

 

 

Thank you so much for the help ^^

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Explorer
Explorer
1,502 Views
Registered: ‎01-23-2018

Re: [Implementation error]

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Hi @syedz @shameera,

 

 

I'm following this guide: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug945-vivado-using-constraints-tutorial.pdf

 

Once I arrive to Primary Clocks I've to put a value to the clock, I suppose this value will be the used on the IP Block Creation, that is, the "Reference Clock Frequency".

 

But on the "Recommend Constraints" section  I have three sys_reset_n as can be seen in the attached image. What should I use or how should I configure them? Where I can find the values requiered? 

 

Now I'm using a design with PCIe Bridge, but I didn't find anything about this value in the provided documentation 

https://www.xilinx.com/support/documentation/ip_documentation/axi_pcie3/v3_0/pg194-axi-bridge-pcie-gen3.pdf

 

 

Thanks

 

 

sys_reset_n.PNG
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