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ihf_maresx
Visitor
Visitor
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Registered: ‎03-31-2016

Implementation fails after adding Aurora6466b Core (Placement issue clock region)

Hello,

 

I have a program which uses several transceivers on a FMC and the ethernet port of my VC707, everything works quite well. Since I tried to add an Aurora64b66b Core to have a transceiver connection over SMA to another VC707, the implementation fails with following message:

 

1.JPG

 

When I have a look on the design, it seems that the mac_engine may collide with the Aurora Core (Region X1Y0, right end):

 

2.JPG

 

Does anyone know how to solve this problem? Do I have to manually place components to the same clock region and if yes how can I do this?

 

I appreciate your help, thank you so much

Best regards

Jan-Philip

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syedz
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3,230 Views
Registered: ‎01-16-2013

@ihf_maresx,

 

Can you please share post opt dcp file which will be located in <project>/<project>.runs/impl_1/**_opt.dcp 

 

--Syed

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ihf_maresx
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Registered: ‎03-31-2016

Hello syedz,

 

thank you for your reply. You find the .dcp File attached.

 

Best regards

Jan-Philip

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syedz
Moderator
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3,132 Views
Registered: ‎01-16-2013

@ihf_maresx,

 

In the shared post opt dcp, I see that you have two GT_CHANNEL instances "sip_vc707_mac_engine_sgmii_0/mac_engine_inst/core_wrapper/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i" & "design_uplink_i/aurora_64b66b_0/inst/design_uplink_aurora_64b66b_0_0_core_i/design_uplink_aurora_64b66b_0_0_wrapper_i/design_uplink_aurora_64b66b_0_0_multi_gt_i/design_uplink_aurora_64b66b_0_0_gtx_inst/gtxe2_i" locked in single clock region (X0Y1) are connected to two different GT_COMMON instance which is causing the error.

 

Note:

1. GT_COMMON and the GT_CHANNEL should always be placed in the same clock region.

2. A clock region has only one GT_COMMON site

 

You need to revisit your code and do the modifications to overcome this error.

 

--Syed

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syedz
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3,115 Views
Registered: ‎01-16-2013

@ihf_maresx,

 

Did the suggestion from my previous post provided any help?

 

--Syed

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venkata
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3,106 Views
Registered: ‎02-16-2010

If both Aurora and ethernet IPs use CPLL for the design, try the following suggestion.
If ethernet and Aurora are targeted to the same GT quad, chose "shared logic in example" option in one of the IP's so that QPLL is instantiated in only one IP. connect the QPLL ports of this IP from the other IP with "Shared logic in core" option.
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