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rpmiller
Observer
Observer
2,909 Views
Registered: ‎10-17-2017

Implementation fails with no error message

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Hi,

I'm using 2017.4.  I recently made some changes to my SDK project, software only, to add SD support.  For some reason, the compiler decided it couldn't find any libraries, and after messing around with the project, I decided to recreate it from scratch.  Amazingly, it compiled.  But I needed to re-export the hardware.  I tried that, but for some reason, the FPGA design was out of date, so I tried to re-run everything.  I didn't change anything on the FPGA side, but now it fails everytime when I try to run implementation with a message in the upper right that says "Design Initialization ERROR".  There is absolutely no log information added after synthesis,so I have no clue what the problem is.  I've spent more time trying to coax Vivado to do what it's supposed to do than to do my actual design work.  Very frustrating.  I'm not sure what to do about this one.

Ryan

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syedz
Moderator
Moderator
3,169 Views
Registered: ‎01-16-2013

@rpmiller,

 

This could be an intermittent issue. If you see the issue consistently then please let us know. 

For now, request you to close this thread by marking your above post as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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rpmiller
Observer
Observer
2,891 Views
Registered: ‎10-17-2017

So, oddly, a complete reboot fixed this.  Sorry to bother everyone with such a mundane issue.  I stand by my comment about Vivado - very frustrating.

 

RPM

syedz
Moderator
Moderator
3,170 Views
Registered: ‎01-16-2013

@rpmiller,

 

This could be an intermittent issue. If you see the issue consistently then please let us know. 

For now, request you to close this thread by marking your above post as "Accept as Solution"

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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johnhd
Adventurer
Adventurer
2,592 Views
Registered: ‎01-08-2018

I just had a similar issue on 2018.1

Wasted several hours trying to get my design to compile - each time implementation failed with no error message.

I tried the suggested trick of rebooting the PC and that didn't help.

It turns out that in my case the problem was caused by changing the implementation name in the Design Runs window - it had the "&" symbol in the name - once this was removed it now compiles.

I share your frustration with Vivado - a message to tell you not to use "&" in the name or an error message that gave you a hint when it failed would have saved a lot of time.

I hope this note helps someone else in the future.

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