07-30-2013 06:57 PM
I'm trying to implement the 16QAM demodulator demo of Xilinx on my own design of QAM modem, but I've been using a Spartan 6 without good results; and according to some readings and the demo itself, I see a Virtex o Kintex fpga is required. So, does anybody know if the fact of use a Spartan could cause my system don't work in a properly way?
Thanks in advance
07-30-2013 11:45 PM
what do you actually mean when you say "without good results"?
Is it not getting implemented?
Is it creating wrong outputs?
Is ist just too slow?
The design uses s number of multipliers.
In a (large enough) Virtex/Kintex device these might all be implemented using DSP48 macros.
Your S6 device might not have that much ressources, so some multipliers might be implemented using the logic fabric, which then is considerably slower.
So, please give more details about the problems you see and your projects goals (specification) so we get the idea what a good result means to you.
Have a nice synthesis
07-31-2013 03:00 PM
first of all, thanks for your reply.
well, happens that when i run the simulation, the output after DDS block (sine and cosine) are not sinusoids, I mean, are just squared signals with a variable amplitud and a lower frequency than the need. I consider i need higher resolution (number of bits or something like that) but even reconfiguring the DDS block according to its PFD from xilinx i didn't get the sine and cosine required
attached are the required signal and the output from the DDS block, repectively.
07-31-2013 03:10 PM
It's not uncommon for people to accidentally post their design implementation question to this forum which is actually for Implementation Tool issues. You may get some good responses here, but I think you would get a wider audience at the General Technical Discussion forum.
07-31-2013 11:41 PM
the sine waves are looking quite good to me, except at the end of the second picture.
There seems to happen some undersampling or critical sampling, which makes the waveform look so strange.
Still this gives no hint about the reasons behind this.
What are the diffrences between a S6 and a V6 implementation of this design?
Do the used blocks (even the DDS-Core) have different specs (e.g. different maximum output frequency) and what Fmax do the synthesized designs reach.
What are your project specs? If the S6 implementation can not reach these, either the FPGA family has to be changed or the design needs to be optimized or adapted so it can work more efficiently on a S6 platform.
But only you can tell, because only you know the numbers.
Have a nice synthesis
08-01-2013 05:02 PM
thanks eilert, the big difference is the frequency (two oscillations per unit required, but I am getting only 1.7 approximately) and the amplitude of the signal obtained is not constant, has small variations.
if could take a look at the following images, you'll see why I say probably I need more resolution, but I don't know exactly what I really need.
the first one image is the sinusoid required (obtained from the LO of the transmitter ) and the second one is the signal from de DDS block
08-01-2013 05:16 PM
and related to the differences, thats what i don't know (okay the amount of resources available, that's for sure), but happens that all papers y found implement this carrier recovery design in a Kintex or Virtex. so I don't know if the blocks of the demo design have any restriction related to the FPGA, for instance S6 need the FIR COMPILER 6.3 block, not previous versions, or perhaps something related to blocks configuration according to the FPGA
thanks a lof for your time!
08-01-2013 11:23 PM
are these Plots obtained from a Matlab/Simulink simulation?
Both seem to show the same sinusoidal signal, only that the second one i sampled at a much lower rate.
The slight amplitude variations come from some odd ratio between teh sampling and output frequency, so the resolution (width of the datatype used) seems to be the same.
So the question is how to get a higher sampling rate.
If these are really Matlab/Simulink simulations, there may be some sampling rate setting simply wrong. (Many blocks have their own sampling rate setting) Or, if you have chosen a different Block version as the original design some settings need to be chosen differently to obtain the desired output signal.
The papers ypou mentioned in your other post were going the easy way, but you are facing the problem to adapt the design to some less capable FPGA family for some reason.
So you need to dig into all teh finer details of the design and the cores it uses.
A lot of datasheet reading and design analysis is required for this.
Work out the design differences and physical constraints of your hardware setup.
Compared to your design goals you then should be able to tell wether it is physically possible to do this adaption or not.
Have a nice synthesis
08-04-2013 02:39 PM
i really appreciate the time you spend here!
well, according to your last post, i already got a good sonudoid (i had to delete the equalizer block for setting the sample period of the DDS block and then, enhance the wave form), now i can say they're sinusoids, but after that, i had to face a new trouble: the output frequency is upper than required, no matter i set the dds (version 5.0) block according to the design equations.
Fout = (Fclk * DeltaTheta)/2^n --- DeltaTheta=phase increment value
n= number of bits in the phase accumulator ( set in 32)
required frequency: two oscillations per unit in simulink
got: three oscilations per unit
if any suggestion, I'd appreciate even more.
thanks in advance, again!!!