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Newbie alcomlab
Newbie
3,140 Views
Registered: ‎02-21-2017

Implementation of lut6_2 on spartan-6 through ISE

Hi, 

 

I try to implement the module below through ISE.

 

module AND (A_0, A_1, B_0, B_1, Y_0, Y_1);
input A_0, A_1, B_0, B_1;
output Y_0, Y_1;
// LUT6_2: 6-input, 2 output Look-Up Table
// 7 Series
// Xilinx HDL Libraries Guide, version 13.1
//.INIT(64'h 0040000006200000) // Specify LUT Contents
LUT6_2 #(
.INIT(64'h 0000000000000000) // Specify LUT Contents
) LUT6_2_inst (
.O6(Y_1), // 1-bit LUT6 output
.O5(Y_0), // 1-bit lower LUT5 output
.I0(A_0), // 1-bit LUT input
.I1(A_1), // 1-bit LUT input
.I2(B_0), // 1-bit LUT input
.I3(B_1), // 1-bit LUT input
.I4(1'b1), // 1-bit LUT input
.I5(1'b1) // 1-bit LUT input (fast MUX select only available to O6 output)
);
// End of LUT6_2_inst instantiation

endmodule

 

I follow the example in page 172 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf 

But when I run the implementation, ISE keep running the "map" procedure over 1hr.

Is there any thing wrong in my code? Should I add some constraints before implementation? 

 

Thanks

 

 

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1 Reply
Professor
Professor
3,111 Views
Registered: ‎08-14-2007

Re: Implementation of lut6_2 on spartan-6 through ISE

How many of these LUT's are you instantiating in the design?

 

If it's not an issue of the design size, it's likely to be a routing issue that causes Map to run so long.  Using both outputs of the LUT6 can create routing congestion, especially if you've got a lot of these instantiated.

-- Gabor
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