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vivek
Explorer
Explorer
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Registered: ‎08-16-2017

Implementation of very large matrix operation in FPGA

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Hello everyone,

 

I am trying to implement a very large matrix multiplication, addition, subtraction and division design on FPGA.

This matrix are large as 16x10 with each element being a 16 bit binary number. 

My challenge here is that every time I multiply two matrices , the size of each element of the resultant matrix increases a lot!

What is the approach to implement this design?

 

 

 

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balkris
Xilinx Employee
Xilinx Employee
1,619 Views
Registered: ‎08-01-2008
this is expected behavior and one of the challenge in dsp application / you can try rounding , truncation. use right shift to make it simple but impact precision
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
1,620 Views
Registered: ‎08-01-2008
this is expected behavior and one of the challenge in dsp application / you can try rounding , truncation. use right shift to make it simple but impact precision
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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vivek
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Registered: ‎08-16-2017

Thank you @balkris.

 

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