07-27-2017 08:23 PM
A design which can very much sit in half of SLR of XC7V2000T device, fails in timing due to routing issue (7000 paths). Whereas the same design when attempted on XC7VX690T device mets timing (just 32 failing paths). We use synplicity to synthesize the design. Used same synthesize option for both device.
On analysis we see that failing path's routing delay is higher (90%) compared to the routing delay in 690T device (80%).
Even after using all the 24 strategies suggested by Vivado, we get the above result. I am just wondering whether there is any special options or strategies that we should use for 2000T device?
07-27-2017 11:32 PM