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vsekar
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Registered: ‎07-11-2017

Implementation on XC7V2000T is bad compared to XC7V690T device inspite of placing the logic in single SLR - any special options need to be used

A design which can very much sit in half of SLR of XC7V2000T device, fails in timing due to routing issue (7000 paths). Whereas the same design when attempted on XC7VX690T device mets timing (just 32 failing paths). We use synplicity  to synthesize the design. Used same synthesize option for both device.

 

On analysis we see that failing path's routing delay is higher (90%) compared to the routing delay in 690T device (80%).

 

Even after using all the 24 strategies suggested by Vivado, we get the above result. I am just wondering whether there is any special options or strategies that we should use for 2000T device?

 

VinothS

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yashp
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Registered: ‎01-16-2013

Hi Vinoths,

I guess your IO placement is playing bigger role here.

Theoretically we can compare that the architecture and the utilization and implementation of design, but in tool small change in RTL/tool settings plays role and here we are changing the entire targeting FPGA so comparing in a way the you have done sound little bit tricky to me.

Apart from that from your post looks like you are more concerned to pack logic in single SLR, if this is ultimately you are trying to then please try P-block (floor planning).

Thanks,
Yash
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vsekar
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Registered: ‎07-11-2017

Yash,
Yes I have used P-block. It was done solely for packing the logic in single SLR to match 690T device. But yes few IOs are in adjacent SLRs.

VinothS
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