UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
248 Views
Registered: ‎11-18-2017

Implementation setting (or strategy) to meet timing closure,

Jump to solution

 

Hello.

Is there a Implementation setting (or strategy) in which implementation runs until the timing is met (there is no negative slack or no timing violance).

Thanks for your help.

0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
188 Views
Registered: ‎11-04-2010

Re: Implementation setting (or strategy) to meet timing closure,

Jump to solution

Hi, @kimjaewon  ,

Yes, the Explore directive has the higher effort level than Default directive and will try different algorithm to get better timing result. 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
5 Replies
Moderator
Moderator
212 Views
Registered: ‎11-04-2010

Re: Implementation setting (or strategy) to meet timing closure,

Jump to solution

Hi, @kimjaewon ,

No. If such Implementation setting exists, the tool will hang in so many situations.

In many situations, the timing violation realted to design should be intervened with source code optimization, correcting constaints...etc.

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
205 Views
Registered: ‎01-22-2015

Re: Implementation setting (or strategy) to meet timing closure,

Jump to solution

@kimjaewon 

All implementation strategies try to run until timing closure is achieved.

When implementation cannot achieve timing closure then it is usually (as hongh says) a result of problems with our coding/design.  The messages and the timing analysis reports produced by implementation help us find and correct the problems with our coding/design.

Achieving timing closure is often a difficult part of FPGA work.  When a design fails timing analysis, we often start by opening the implemented design and looking at the timing paths that have the Worst Negative Slack (WNS).

UG906 is a good document about achieving timing closure as is UG1292.

Mark

Adventurer
Adventurer
194 Views
Registered: ‎11-18-2017

Re: Implementation setting (or strategy) to meet timing closure,

Jump to solution

 

In the (Vivado) Implementation settings, I changed the Options strategy from Vivado Implementation Defaults to Performance_Explore.

Then, after I re-implemented, the negative slacks all disappeared (although the elapsed time increased). 

I guess changing the settings made the difference.

0 Kudos
Moderator
Moderator
189 Views
Registered: ‎11-04-2010

Re: Implementation setting (or strategy) to meet timing closure,

Jump to solution

Hi, @kimjaewon  ,

Yes, the Explore directive has the higher effort level than Default directive and will try different algorithm to get better timing result. 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
Highlighted
172 Views
Registered: ‎01-22-2015

Re: Implementation setting (or strategy) to meet timing closure,

Jump to solution

@kimjaewon 

You were lucky this time.  Rarely, timing closure problems can be solved by only changing the implementation settings/strategy.

Mark