07-24-2013 03:11 AM
I am trying to develop my vhdl project for GR-CPCI-XC4V LEON Compact-PCI Development board. Simulation works fine, and implementation too, but the component does not work as expected. The problem is that if I implement the component with the option keep hierarchy "yes" it works properly. Why?
07-24-2013 09:53 AM
When you set KEEP_HIERARCHY to "YES" its preserves the hierarchy of your design.
When you set it as "NO" its flattern the hierarchy and optimization has been done at the boundries of the modules.
Might be the optimization at boundries is one of the reason for the issue.
To know about KEEP_HIERARCHY in detail please refer this document:
07-25-2013 06:53 PM
Did you compare the timing resutl of the two implementation. Especially for hold problems. Maybe "keep" satisfy your hold time and "flattern" optimized your timing too much led to hold problem!
07-26-2013 05:11 AM