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3,252 Views
Registered: ‎07-24-2013

Implementation works fine only with keep hierarchy "yes"

Hi,

I am trying to develop my vhdl project for GR-CPCI-XC4V LEON Compact-PCI Development board. Simulation works fine, and implementation too, but the component does not work as expected. The problem is that if I implement the component with the option  keep hierarchy "yes" it works properly. Why?

 

Thanks

 

Alessandro Vallero

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3 Replies
Moderator
Moderator
3,238 Views
Registered: ‎01-16-2013

Re: Implementation works fine only with keep hierarchy "yes"

Hello,

 

When you set KEEP_HIERARCHY to "YES" its preserves the hierarchy of your design.

When you set it as "NO" its flattern the hierarchy and optimization has been done at the boundries of the modules.

 

Might be the optimization at boundries is one of the reason for the issue.

 

To know about KEEP_HIERARCHY in detail please refer this document:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/cgd.pdf

 

Regards,

Yash 

 

 

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Explorer
Explorer
3,217 Views
Registered: ‎04-28-2013

Re: Implementation works fine only with keep hierarchy "yes"

Did you  compare the timing resutl of the two implementation. Especially for hold problems.  Maybe "keep" satisfy your hold time and "flattern" optimized your timing too much led to hold problem!

 

 

nonsense
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Community Manager
Community Manager
3,211 Views
Registered: ‎06-14-2012

Re: Implementation works fine only with keep hierarchy "yes"

I assume this is a xst option. Did you try to use map switch ignore_keep_hierarchy? Are there any timing violations in the testcase?
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