cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
20,159 Views
Registered: ‎11-11-2013

ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I'm using vivado 2014.4 and win7 64bit for my zynq design.  Previously, the design is good. I made some revisions. Then I came across the problem.

If the synthesis strategies option is flow_runtime_optimatized(Vivadio synthesis 2014), everything works

If the synthesis  strategies option is default options (the synthesis settings are shown in the picture), Synthesis is still fine, but the implementation failed. Some of the errror msg is shown below.

 

The error message shows there are unconnected pins on axi_interconnect_1. The connections between AXI master from my own IP(it is the axi port from a DataMover IP) and axi_interconnected is shown in the attached picture.

 

The synthesis schematic is also checked. The connections of the axi_interconnect have some pins unconnected as shown in the picture (interconnect_schematic_synth.PNG). The connections of my IP are good, but it misses some pins (like _arready, _rvalid, _ruser, _bid...).  The master AXI port in my port is from the data mover IP. By default, the data mover IP doesn't have these missed pins. The AXI port on my IP declares these missed pins, but actually they are not connected to any inside my IP. 

Btw, previously, the project works well in my design. But now it doesn't.

 

 I also check the connections of the axi_interconnect when synthesis strategies option is flow_runtime_optimatized, the schematic show all pins are connected. 

 

Please help. Thx.

Sam

 

 

 

ImplementationOpt Design[Opt 31-67] Problem: A LUT1 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_top_level_i/Zynq_Processing_System/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q[3]_i_1__0.
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_top_level_i/Zynq_Processing_System/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/access_is_incr_q_i_1__0.
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_top_level_i/Zynq_Processing_System/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/access_is_incr_q_i_1__0.
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_top_level_i/Zynq_Processing_System/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/command_ongoing_i_2__0.
[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_top_level_i/Zynq_Processing_System/axi_interconnect_1/s00_couplers/auto_pc/inst/gen_axi4_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/size_mask_q[1]_i_1__0.
[Opt 31-67] Problem:

BlockDesign.PNG
interconnect_schematic_synth.PNG
myIP_schematic_synth.PNG
SynthesisSettings.PNG
0 Kudos
28 Replies
Highlighted
Teacher
Teacher
20,105 Views
Registered: ‎03-31-2012

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

opt_design has a bug which causes this missing cell problem. You can try a different opt_design option (like -directive Explore) and see if that helps. Another option is to turn-off opt_design and add phys_opt_design later in the flow. I hope they will address this problem in the upcoming 2015.1 version (which is due 4/23 apparently)
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Highlighted
Explorer
Explorer
20,059 Views
Registered: ‎11-11-2013

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

 

Hi Muzaffer

THx for your reply. 

I tried implementation with opt_design option -directive Explore, it didn't work.

Aslo I disabled the opt_design and enabled phys_opt_design, it still has the same error in the implementation.

 

I would try to delete the pins related  _AR_(like _arready, etc. ) and _R_ (like _rdata, _rid, etc.) pins in the AXI4 port in my IP. The data mover ip doesn't contains thes pins. I want  to see whether it works this way.

 

Hopefully, the new vivado version will help. 

0 Kudos
Highlighted
Adventurer
Adventurer
19,553 Views
Registered: ‎12-10-2014

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I have the exact same problem, but for me it works in vivado 2014.4, but not in vivado 2015.2; so it looks like 2015 did not fix the bug in opt_design;

 

looks like I will have to stick with 2014.4 until this bug is fixed;  I wonder how many other users have come across this bug?

0 Kudos
Highlighted
Explorer
Explorer
11,448 Views
Registered: ‎09-13-2011

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Just come across it in 2017.1:

 

[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I5, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: gen_transceiver_core.eth_1000basex_phy_inst/U0/pcs_pma_block_i/gig_ethernet_pcs_pma_0_core/gpcs_pma_inst/HAS_MANAGEMENT.MDIO/MDIO_INTERFACE_1/ADDRESS_MATCH_i_2.

 

The management interface is not connected since the core in the other end is not there, but I think it should be able to cope with this and just trim the logic.

 

0 Kudos
Highlighted
Observer
Observer
10,950 Views
Registered: ‎11-08-2010

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I'll add my voice to this as well - just encountered the issue in 2016.2

0 Kudos
Highlighted
Visitor
Visitor
10,855 Views
Registered: ‎06-01-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

[Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: design_1_i/TestAXIMaster_0/U0/generate_32b_data_fifo.read_data_fifo_inst/DataOut[31]_i_2__0.

 

Count me in, vivado 2016.4.... I spent the whole day adding something to my design to end up with this... sigh....

 

0 Kudos
Highlighted
Visitor
Visitor
10,611 Views
Registered: ‎11-30-2016

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Me too. 2017.2
0 Kudos
Highlighted
10,419 Views
Registered: ‎07-04-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

2017.2, The bug is still there......

0 Kudos
Highlighted
Moderator
Moderator
10,348 Views
Registered: ‎01-16-2013

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

x.zhang@voco.com,

 

Can you please share your post synthesis design checkpoint file (.dcp) to debug the issue?

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
7,852 Views
Registered: ‎07-26-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Same [Opt 31-67] errors here. Persistent for two days now. I am now going through our vendor. We have prototype hardware  going to manufacturer but the design is halted until this is fixed.

0 Kudos
Highlighted
Visitor
Visitor
7,784 Views
Registered: ‎05-10-2010

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Same problem here.

 

  • [Opt 31-67] Problem: A LUT5 cell in the design is missing a connection on input pin I4, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: map_pcie_BAR0_queue/cpltr_fifo_data_in[0][121]_i_2.

Wasting a lot of time on trying to get around this.

0 Kudos
Highlighted
Visitor
Visitor
7,745 Views
Registered: ‎08-08-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Same problem ! 2017.2 ..

0 Kudos
Highlighted
Explorer
Explorer
7,494 Views
Registered: ‎05-01-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I packed iobuf.vhd into ip, and used it to wrapper a tri-state GPIO , hit by this error as well

 

https://www.xilinx.com/Attachment/iobuf.vhd

0 Kudos
Highlighted
Observer
Observer
7,328 Views
Registered: ‎09-28-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

same problem with vdma and interconnect do you have a solution

0 Kudos
Highlighted
Observer
Observer
7,178 Views
Registered: ‎09-10-2016

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Getting this problem in 2017.3.  Exact same design works just fine in 2017.2 (actually runs on HW)

 

ERROR: [Opt 31-67] Problem: A LUT4 cell in the design is missing a connection on input pin I2, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic.

 

The synthesized schematics appears to be correct and is identical in 2017.2 /.3.

The signal in question originates at FIFO18.EMPTY, goes through LUT1 inverter where it becomes a net called  'valid' and from there it goes to quite a few places including the problematic LUT4.I2 input. The net also has a MARK_DEBUG attribute on it although there are no debug cores in the design.

 

0 Kudos
Highlighted
6,968 Views
Registered: ‎03-03-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I am also seeing this issue in 2017.3, where the same design implements just fine in 2017.2.

Tim

0 Kudos
Highlighted
Moderator
Moderator
6,918 Views
Registered: ‎02-07-2008

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

The error is a result of Vivado attempting to push a LUT1 inverter into upstream logic, but not successfully re-connecting this. This is currently under investigation by the factory, due to be fixed in a future version of Vivado.

 

A possible work around is to set a DONT_TOUCH property on the LUT1 driving the LUT mentioned in the error. This can be found from the open synthesized design checkpoint, e.g.

 

set_property DONT_TOUCH true [get_cells <lut1_name>]

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
6,534 Views
Registered: ‎11-17-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

The set_property DONT_TOUCH true [get_cells LUTx] workaround didn't work for me. Still seeing the same issue.

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
6,524 Views
Registered: ‎09-20-2012

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Hi @1siemens

 

Is it possible to share the post synthesis DCP? 

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos
Highlighted
Visitor
Visitor
5,355 Views
Registered: ‎11-17-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

No, I deleted the block that was giving me errors and started over and didn't receive the error again.

 

I think the cause was that I had an Aurora block and selected "additional transceiver control and status ports" and attached an ILA to those ports, and then unselected that box while the ports were still connected to the ILA. You can try to recreate that behavior, but I'm unsure if that was the cause or just happened to occur at the same time.

0 Kudos
Highlighted
Adventurer
Adventurer
5,010 Views
Registered: ‎09-18-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Ehm,

I have noticed that when I generate the Block Diagram globally. This problem is removed, however when I generate the block diagram as IPs I get this error in vivado 2017.3.

 

 

0 Kudos
Highlighted
Adventurer
Adventurer
4,974 Views
Registered: ‎09-18-2017

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Hello!

 

@muzaffer

I got this on vivado 2017.3

 

is there a fix for this bug?

 

Generating every module globally takes a huge amount of time when I want to debug 1 specific module out of 100 modules.?

 

Is there a way to resolve this problem and run it as OOC?

 

 

0 Kudos
Highlighted
Scholar
Scholar
4,843 Views
Registered: ‎05-31-2012

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Have the same problem in Vivado 2017.3
I used ila in my design, then i removed all debug cores and made some changes to sources, now i see the error
The error is inside an axis data fifo component
0 Kudos
Highlighted
Scholar
Scholar
4,838 Views
Registered: ‎05-31-2012

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I found a workaround, i removed some mark_debug attributes from the source code of a component directly connected to the fifo, now it works

0 Kudos
Highlighted
Visitor
Visitor
4,174 Views
Registered: ‎04-19-2018

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Hi All,

 

I am using vivado 2017.4 version, Still i am getting this error

ERROR: [Opt 31-67] Problem: A LUT3 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_ila_0/inst/ila_core_inst/probeDelay1[0]_i_1.

 

This is only accounting while using ILA probes, after post synthesis, ie using ILA in batch mode.

i cross verified in the schematic, all are LUT3 cells are connected properly.

 

can anybody has a solution for this ?

 

Regards,

Ajay

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
4,163 Views
Registered: ‎05-08-2012

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Hi @ajaysim. Can you start a new post, and upload the post-synthesis DCP? The issue of this post (inverter pushing) was resolved in 2017.4.

 

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

---------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Visitor
Visitor
4,016 Views
Registered: ‎05-28-2018

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

I am using vivado 2017.4 version, Still i am getting this error

 

[Opt 31-67] Problem: A LUT4 cell in the design is missing a connection on input pin I0, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: u_sfp_decode/u_sfpdp_ip/sfp2_sfpdp_core/decode_packet_inst/reset_n_inv1.

 

 

0 Kudos
Highlighted
Moderator
Moderator
3,998 Views
Registered: ‎02-07-2008

Re: ImplementationOpt Design[Opt 31-67] Problem for AXI bus between data mover ip and axi interconnect

Hi @shineui1, please start a new topic, uploading the post-synthesis DCP, if possible.

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos