10-31-2018 01:06 PM - edited 10-31-2018 01:08 PM
The implementation cycle is time costly for many engineers where we often always rebuild the same and when the synthesis tools change version its tedious to rerun and rebuild all to fit the new synthesis results.
there are things one want but has to redo each time that it would be nice to have in a generic form and available for all:
OS specification project:
- the ability to send and receive files to the FPGA using the USB port
- the ability to send and receive files to the FPGA using the UDP port
- the ability to see real time captured data from test points returned in tables
- turning the tables to excel like graphs emulating the oscilloscope screen
- the ability to run processor code using macro tiles provided
this will allow controlling data inside the FPGA with code making it far easier to develop ones firmware
10-31-2018 01:34 PM
11-01-2018 07:35 PM - edited 11-02-2018 06:32 PM
Thanks for asking for more details its is always a pleasure to detail our work, basically we need many volunteers to help find flaws and debug for the final release
So more details..
Basically the FPGA offers the possibility to select the data size as one wants so the idea was to perform arithmetics on 1 bit scalable tiles. When that worked we realized that instead of one data 1..N size once can also have
A7..0 B7..0 for A+B for ome 8 bit operation
A3..0 B3..0 C3..0 D3..0 for A+B C+D with 2 4 bits operation
A1..0 B1..0 C1..0 D1..0 E1..0 F1..0 G1..0 H1..0 A+B C+D E+F G+H with 4 2 bits operation
A5..0 B5..0 C1..0 D1..0 for A+B C+D with a 6bits and 2 bits operation
this is not limited to the addition but one can have different operations..
The implications are tremendous because that means one can have several codes running concurently using those tiles as an extendable ALU. What were testing now is how to add addressing instructions and a basic operating system principle so people can use the tiles and OS to have their application developped on FPGA and not worry on the sequential aspects
We provide all the on board sequential sytem for file up and download form the internet to the FPGA and then the ability to deserve that data using concurrent code ("as workers") so the user can just focus on the block he is building ~