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Explorer
Explorer
438 Views
Registered: ‎04-12-2012

Inbuilt randomness in Vivado Implementation ?

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Hello,

Do the P&R algorithms inside Vivado containt any inbuilt randomness in them ?

Would it be possible to get 2 different results when compiling the same desgin twice (given the same Vivado version) ? 

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Moderator
Moderator
344 Views
Registered: ‎01-16-2013

Re: Inbuilt randomness in Vivado Implementation ?

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Hi All,

I have gone through complete discussion.
As mentioned by @allanherriman if the inputs for multiple runs are identical (Inputs includes RTL, IP versions, XDC, Tool level settings etc.) then run results should be identical. That is expected behavior from Vivado Synthesis and Implementation.

If keeping everything same you are getting different results, I would request if you can share the test case with us for further investigation?

Let us know, we will form channel (secured one) to get the files without being uploaded at public domain.

Thanks,
Yash
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Scholar drjohnsmith
Scholar
426 Views
Registered: ‎07-09-2009

Re: Inbuilt randomness in Vivado Implementation ?

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There is much debate upon this.

 

As a background, the old ISE used to have a definate part using "artificial aneeling", and the  bit file had other meta data in it, which changed on each run, machine to machine etc.

 

Now in theory, the Vivado does not have artificail aneeling, nore the other features,

     so the conclusion was, it woudl always produce the sam eoutput form no matter what machine, from the same source files.

BUT

 

a lot of us users have seen this to be at best less than true.

 

BUT

As long as the design is meeting constraints, we are happy

   you see Vivaodo is a ASIC type flow, where the tools just run till the constrainst are meet, and then stop.

 

The suspicion is that the aim is for the tools to always produce the sam ebit file fomr the same source,

  

But then things like

Vivado cache

Out of context

different veriosn of the tools,

different number of cores allocated to a job,

different OS,

pre placed, locked blocks

all seem to affect the resultant bit file,

 

BUT

 

as said, and I can not say this any louder,

 

provided the design meets constraints, then who worries about actual routing insode the chip !

 

 

 

Explorer
Explorer
414 Views
Registered: ‎04-12-2012

Re: Inbuilt randomness in Vivado Implementation ?

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"provided the design meets constraints, then who worries about actual routing insode the chip !"

You might care...

As far as I understand - Vivado attempts P&R a finite number of times before it decides that meeting timing is impossible and terminates the process with negative slack on one or more paths.  

Now, suppose a design is VERY marginal and Vivado DOES have some inherent pseudorandomness in its algorithms - In this case on some runs the tool WILL be able to meet timing and fail on others...

Can someone from Xilinx give a definitive answer ?

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Scholar drjohnsmith
Scholar
377 Views
Registered: ‎07-09-2009

Re: Inbuilt randomness in Vivado Implementation ?

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good point,
Suggest you Look at it the other way

suggest an algorithm which will guarantee identical bit file for same code with all the other variations highlighted,

Also as a point of practicality,

if things are that marginal, you are in problems,

not least the next version of the tools is not guaranteed to use the same Algorithums, and timing files for chips change over time.

If that;s where you are at, I for one can appreciate it, been there, very frustrating.


349 Views
Registered: ‎01-08-2012

Re: Inbuilt randomness in Vivado Implementation ?

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There is no inherent pseudorandomness in Vivado's algorithms, in the sense that you will get identical results every time given identical inputs.  (This has been true for all of the test cases I've tried.)

Note that this does not preclude the internal use of Monte Carlo techniques; however, if employed, they apparently use the same seed each run.

Moderator
Moderator
345 Views
Registered: ‎01-16-2013

Re: Inbuilt randomness in Vivado Implementation ?

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Hi All,

I have gone through complete discussion.
As mentioned by @allanherriman if the inputs for multiple runs are identical (Inputs includes RTL, IP versions, XDC, Tool level settings etc.) then run results should be identical. That is expected behavior from Vivado Synthesis and Implementation.

If keeping everything same you are getting different results, I would request if you can share the test case with us for further investigation?

Let us know, we will form channel (secured one) to get the files without being uploaded at public domain.

Thanks,
Yash
341 Views
Registered: ‎01-08-2012

Re: Inbuilt randomness in Vivado Implementation ?

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See also AR#61599 "Vivado Implementation - Discussion of tool repeatability" and this thread "Vivado 2015.2 Producing Inconsistent Checksum" in which the results of some repeatability tests were discussed.

Moderator
Moderator
336 Views
Registered: ‎03-16-2017

Re: Inbuilt randomness in Vivado Implementation ?

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Hi @shaikon ,

If repeatability is absolutely critical to your design environment, the following can help maximize repeatability:

Running in single-threaded mode. 

Apply this command set_param general.maxThreads 1   and then run. 

Regards,
hemangd

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Explorer
Explorer
319 Views
Registered: ‎04-12-2012

Re: Inbuilt randomness in Vivado Implementation ?

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"I would request if you can share the test case with us for further investigation? 
Let us know, we will form channel (secured one) to get the files without being uploaded at public domain."

I'll test the feasability of this approach with the customer.

Thank you.