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Observer
Observer
639 Views
Registered: ‎02-02-2017

Incorrect net width in netlist

Hello, I am having an issue with a design and checking implementation I have notice that, in netlist window, the width of signals is incorrect. In my design, I have some wires declared with a width of 13. All bits of this wires are used because the wires comes from ADC and go to my control.

wire signed [12:0] adc_ir, adc_is, adc_it, adc_idc, adc_ir_conv, adc_it_conv; /*  13 bits adc */

When I check the netlist, the width of this signals is different of the width declared.

image.png

Honestly, I'm not sure if this number that I see in the netlist is corresponding with the width of the bus, but I think I'm right, but I'm not sure. can anyone explain it me? Or how I have to read the netlist? Thanks!

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Teacher
Teacher
613 Views
Registered: ‎07-09-2009

Re: Incorrect net width in netlist

I would suggest that your design is being optimised,
Simulate and see if the design works,

If it does, then the tools are being clever,

If not , check your code , again in simulation as its most probable you have made a mistake,
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Observer
Observer
566 Views
Registered: ‎02-02-2017

Re: Incorrect net width in netlist

Thanks for the answer, but design works fine and I'm sure signals uses at least 12 bits because this signals are sended to other device and I can see them. Maybe that is not the width of the signals?

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Teacher
Teacher
560 Views
Registered: ‎07-09-2009

Re: Incorrect net width in netlist

By works, do you mean in simulation ?

Its only simulation that you can check the corner cases in your design, and can look in detail at how the design is working,

Simulate, and look at those signals,


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Observer
Observer
554 Views
Registered: ‎02-02-2017

Re: Incorrect net width in netlist

By work, I mean the design is been tested in production, with no major bugs. Anyway, I think that I see is not that I think, because according the schematic of adc_it, only one bit goes to SENSE module? This module compute the average...

 

image.png

Maybe this net is splitted in several nets with different names? Thanks!

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Teacher
Teacher
536 Views
Registered: ‎07-09-2009

Re: Incorrect net width in netlist

If you have not simulated the corner cases, then you are running with fingers crossed no one finds the bug in the field.

good luck with that as a strategy,
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Observer
Observer
535 Views
Registered: ‎02-02-2017

Re: Incorrect net width in netlist

Can you show the exact line of my posts where I say "my design is not tested"? I'm telling you that the design works correctly, if the width in netlist is correct, or is that I understand, nothing will works. Anyway, thanks.

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Teacher
Teacher
533 Views
Registered: ‎07-09-2009

Re: Incorrect net width in netlist

I asked about testing in simulation 

you replied

"By work, I mean the design is been tested in production"

 

 

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Xilinx Employee
Xilinx Employee
437 Views
Registered: ‎05-22-2018

Re: Incorrect net width in netlist

Hi @pablo_trujillo ,

You can wor around the issue by applying DONT_TOUCH attribute on nets. For syntax please check page no.49 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug901-vivado-synthesis.pdf 

Thanks,

Raj

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Observer
Observer
328 Views
Registered: ‎02-02-2017

Re: Incorrect net width in netlist

Hello Raj!

I used this instruction and now the signals has the correct size, but I don't understand how the module can compute the average with only one bit of this signal. I still working for understand that. Thanks!!!

 

Greetings

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Xilinx Employee
Xilinx Employee
221 Views
Registered: ‎05-22-2018

Re: Incorrect net width in netlist

Hi @pablo_trujillo ,

That i am too not sure as might be coming from sytnhesis itself. For proper analysis we will be needing the test case at our end.

Till then DONT_TOUCH is valid work around.

Thanks.,

Raj

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